Searched refs:TC1 (Results 1 – 12 of 12) sorted by relevance
| /loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/ |
| D | saml21e15b.h | 424 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21e16b.h | 424 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21e17b.h | 424 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21e18b.h | 424 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21g16b.h | 424 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21g17b.h | 424 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21g18b.h | 424 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21j16b.h | 432 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
562 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
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| D | saml21j17b.h | 432 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
562 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
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| D | saml21j18b.h | 432 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
562 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
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| D | saml21j18bu.h | 432 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ macro
562 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ macro
567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
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| /loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/ |
| D | tal.h | 726 uint32_t TC1:1; /*!< bit: 4 TC1 Interrupt CPU Select */ member
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