1 /*
2 * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define LOG_DOMAIN flash_stm32g4
8 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
9 #include <zephyr/logging/log.h>
10 LOG_MODULE_REGISTER(LOG_DOMAIN);
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <string.h>
15 #include <zephyr/drivers/flash.h>
16 #include <zephyr/sys/barrier.h>
17 #include <zephyr/init.h>
18 #include <soc.h>
19 #include <stm32_ll_system.h>
20
21 #include "flash_stm32.h"
22
23 #define STM32G4_SERIES_MAX_FLASH 512
24 #define BANK2_OFFSET (KB(STM32G4_SERIES_MAX_FLASH) / 2)
25
26 /*
27 * offset and len must be aligned on 8 for write,
28 * positive and not beyond end of flash
29 */
flash_stm32_valid_range(const struct device * dev,off_t offset,uint32_t len,bool write)30 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
31 uint32_t len,
32 bool write)
33 {
34
35 #if defined(FLASH_STM32_DBANK) && (CONFIG_FLASH_SIZE < STM32G4_SERIES_MAX_FLASH)
36 /*
37 * In case of bank1/2 discontinuity, the range should not
38 * start before bank2 and end beyond bank1 at the same time.
39 * Locations beyond bank2 are caught by flash_stm32_range_exists.
40 */
41 if ((offset < BANK2_OFFSET) && (offset + len > FLASH_SIZE / 2)) {
42 return 0;
43 }
44 #endif
45
46 if (write && !flash_stm32_valid_write(offset, len)) {
47 return false;
48 }
49 return flash_stm32_range_exists(dev, offset, len);
50 }
51
flush_cache(FLASH_TypeDef * regs)52 static inline void flush_cache(FLASH_TypeDef *regs)
53 {
54 if (regs->ACR & FLASH_ACR_DCEN) {
55 regs->ACR &= ~FLASH_ACR_DCEN;
56 /* Datasheet: DCRST: Data cache reset
57 * This bit can be written only when the data cache is disabled
58 */
59 regs->ACR |= FLASH_ACR_DCRST;
60 regs->ACR &= ~FLASH_ACR_DCRST;
61 regs->ACR |= FLASH_ACR_DCEN;
62 }
63
64 if (regs->ACR & FLASH_ACR_ICEN) {
65 regs->ACR &= ~FLASH_ACR_ICEN;
66 /* Datasheet: ICRST: Instruction cache reset :
67 * This bit can be written only when the instruction cache
68 * is disabled
69 */
70 regs->ACR |= FLASH_ACR_ICRST;
71 regs->ACR &= ~FLASH_ACR_ICRST;
72 regs->ACR |= FLASH_ACR_ICEN;
73 }
74 }
75
write_dword(const struct device * dev,off_t offset,uint64_t val)76 static int write_dword(const struct device *dev, off_t offset, uint64_t val)
77 {
78 volatile uint32_t *flash = (uint32_t *)(offset + FLASH_STM32_BASE_ADDRESS);
79 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
80 #if defined(FLASH_STM32_DBANK)
81 bool dcache_enabled = false;
82 #endif /* FLASH_STM32_DBANK */
83 uint32_t tmp;
84 int rc;
85
86 /* if the control register is locked, do not fail silently */
87 if (regs->CR & FLASH_CR_LOCK) {
88 LOG_ERR("CR locked");
89 return -EIO;
90 }
91
92 /* Check that no Flash main memory operation is ongoing */
93 rc = flash_stm32_wait_flash_idle(dev);
94 if (rc < 0) {
95 return rc;
96 }
97
98 /* Check if this double word is erased and value isn't 0.
99 *
100 * It is allowed to write only zeros over an already written dword
101 * See 3.3.7 in reference manual.
102 */
103 if ((flash[0] != 0xFFFFFFFFUL ||
104 flash[1] != 0xFFFFFFFFUL) && val != 0UL) {
105 LOG_ERR("Word at offs %ld not erased", (long)offset);
106 return -EIO;
107 }
108
109 #if defined(FLASH_STM32_DBANK)
110 /*
111 * Disable the data cache to avoid the silicon errata ES0430 Rev 7 2.2.2:
112 * "Data cache might be corrupted during Flash memory read-while-write operation"
113 */
114 if (regs->ACR & FLASH_ACR_DCEN) {
115 dcache_enabled = true;
116 regs->ACR &= (~FLASH_ACR_DCEN);
117 }
118 #endif /* FLASH_STM32_DBANK */
119
120 /* Set the PG bit */
121 regs->CR |= FLASH_CR_PG;
122
123 /* Flush the register write */
124 tmp = regs->CR;
125
126 /* Perform the data write operation at the desired memory address */
127 flash[0] = (uint32_t)val;
128 flash[1] = (uint32_t)(val >> 32);
129
130 /* Wait until the BSY bit is cleared */
131 rc = flash_stm32_wait_flash_idle(dev);
132
133 /* Clear the PG bit */
134 regs->CR &= (~FLASH_CR_PG);
135
136 #if defined(FLASH_STM32_DBANK)
137 /* Reset/enable the data cache if previously enabled */
138 if (dcache_enabled) {
139 regs->ACR |= FLASH_ACR_DCRST;
140 regs->ACR &= (~FLASH_ACR_DCRST);
141 regs->ACR |= FLASH_ACR_DCEN;
142 }
143 #endif /* FLASH_STM32_DBANK */
144
145 return rc;
146 }
147
erase_page(const struct device * dev,unsigned int offset)148 static int erase_page(const struct device *dev, unsigned int offset)
149 {
150 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
151 uint32_t tmp;
152 int rc;
153 int page;
154
155 /* if the control register is locked, do not fail silently */
156 if (regs->CR & FLASH_CR_LOCK) {
157 LOG_ERR("CR locked");
158 return -EIO;
159 }
160
161 /* Check that no Flash memory operation is ongoing */
162 rc = flash_stm32_wait_flash_idle(dev);
163 if (rc < 0) {
164 return rc;
165 }
166
167 #if defined(FLASH_STM32_DBANK)
168 bool bank_swap;
169 /* Check whether bank1/2 are swapped */
170 bank_swap = (LL_SYSCFG_GetFlashBankMode() == LL_SYSCFG_BANKMODE_BANK2);
171
172 if ((offset < (FLASH_SIZE / 2)) && !bank_swap) {
173 /* The pages to be erased is in bank 1 */
174 regs->CR &= ~FLASH_CR_BKER_Msk;
175 page = offset / FLASH_PAGE_SIZE;
176 LOG_DBG("Erase page %d on bank 1", page);
177 } else if ((offset >= BANK2_OFFSET) && bank_swap) {
178 /* The pages to be erased is in bank 1 */
179 regs->CR &= ~FLASH_CR_BKER_Msk;
180 page = (offset - BANK2_OFFSET) / FLASH_PAGE_SIZE;
181 LOG_DBG("Erase page %d on bank 1", page);
182 } else if ((offset < (FLASH_SIZE / 2)) && bank_swap) {
183 /* The pages to be erased is in bank 2 */
184 regs->CR |= FLASH_CR_BKER;
185 page = offset / FLASH_PAGE_SIZE;
186 LOG_DBG("Erase page %d on bank 2", page);
187 } else if ((offset >= BANK2_OFFSET) && !bank_swap) {
188 /* The pages to be erased is in bank 2 */
189 regs->CR |= FLASH_CR_BKER;
190 page = (offset - BANK2_OFFSET) / FLASH_PAGE_SIZE;
191 LOG_DBG("Erase page %d on bank 2", page);
192 } else {
193 LOG_ERR("Offset %d does not exist", offset);
194 return -EINVAL;
195 }
196 #else
197 page = offset / FLASH_PAGE_SIZE;
198 LOG_DBG("Erase page %d", page);
199 #endif
200
201 /* Set the PER bit and select the page you wish to erase */
202 regs->CR |= FLASH_CR_PER;
203 regs->CR &= ~FLASH_CR_PNB_Msk;
204 regs->CR |= (page << FLASH_CR_PNB_Pos);
205
206 /* Set the STRT bit */
207 regs->CR |= FLASH_CR_STRT;
208
209 /* flush the register write */
210 tmp = regs->CR;
211
212 /* Wait for the BSY bit */
213 rc = flash_stm32_wait_flash_idle(dev);
214
215 flush_cache(regs);
216
217 #ifdef FLASH_STM32_DBANK
218 regs->CR &= ~(FLASH_CR_PER | FLASH_CR_BKER);
219 #else
220 regs->CR &= ~(FLASH_CR_PER);
221 #endif
222
223 return rc;
224 }
225
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)226 int flash_stm32_block_erase_loop(const struct device *dev,
227 unsigned int offset,
228 unsigned int len)
229 {
230 unsigned int address = offset;
231 int rc = 0;
232
233 for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {
234 rc = erase_page(dev, address);
235 if (rc < 0) {
236 break;
237 }
238 }
239
240 return rc;
241 }
242
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)243 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
244 const void *data, unsigned int len)
245 {
246 int i, rc = 0;
247
248 for (i = 0; i < len; i += 8, offset += 8) {
249 rc = write_dword(dev, offset, ((const uint64_t *) data)[i>>3]);
250 if (rc < 0) {
251 return rc;
252 }
253 }
254
255 return rc;
256 }
257
flash_stm32_option_bytes_write(const struct device * dev,uint32_t mask,uint32_t value)258 int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
259 uint32_t value)
260 {
261 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
262 int rc;
263
264 if (regs->CR & FLASH_CR_OPTLOCK) {
265 return -EIO;
266 }
267
268 if ((regs->OPTR & mask) == value) {
269 return 0;
270 }
271
272 rc = flash_stm32_wait_flash_idle(dev);
273 if (rc < 0) {
274 return rc;
275 }
276
277 regs->OPTR = (regs->OPTR & ~mask) | value;
278 regs->CR |= FLASH_CR_OPTSTRT;
279
280 /* Make sure previous write is completed. */
281 barrier_dsync_fence_full();
282
283 rc = flash_stm32_wait_flash_idle(dev);
284 if (rc < 0) {
285 return rc;
286 }
287
288 return 0;
289 }
290
flash_stm32_option_bytes_read(const struct device * dev)291 uint32_t flash_stm32_option_bytes_read(const struct device *dev)
292 {
293 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
294
295 return regs->OPTR;
296 }
297
298 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
299
300 /*
301 * Remark for future development implementing Write Protection for the L4 parts:
302 *
303 * STM32L4 allows for 2 write protected memory areas, c.f. FLASH_WEP1AR, FLASH_WRP1BR
304 * which are defined by their start and end pages.
305 *
306 * Other STM32 parts (i.e. F4 series) uses bitmask to select sectors.
307 *
308 * To implement Write Protection for L4 one should thus add a new EX_OP like
309 * FLASH_STM32_EX_OP_SECTOR_WP_RANGED in stm32_flash_api_extensions.h
310 */
311
312 #endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */
313
314 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
flash_stm32_get_rdp_level(const struct device * dev)315 uint8_t flash_stm32_get_rdp_level(const struct device *dev)
316 {
317 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
318
319 return (regs->OPTR & FLASH_OPTR_RDP_Msk) >> FLASH_OPTR_RDP_Pos;
320 }
321
flash_stm32_set_rdp_level(const struct device * dev,uint8_t level)322 void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
323 {
324 flash_stm32_option_bytes_write(dev, FLASH_OPTR_RDP_Msk,
325 (uint32_t)level << FLASH_OPTR_RDP_Pos);
326 }
327 #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
328
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)329 void flash_stm32_page_layout(const struct device *dev,
330 const struct flash_pages_layout **layout,
331 size_t *layout_size)
332 {
333 ARG_UNUSED(dev);
334
335 #if defined(FLASH_STM32_DBANK) && (CONFIG_FLASH_SIZE < STM32G4_SERIES_MAX_FLASH)
336 #define PAGES_PER_BANK ((FLASH_SIZE / FLASH_PAGE_SIZE) / 2)
337 static struct flash_pages_layout stm32g4_flash_layout[3];
338
339 if (stm32g4_flash_layout[0].pages_count == 0) {
340 /* Bank1 */
341 stm32g4_flash_layout[0].pages_count = PAGES_PER_BANK;
342 stm32g4_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
343 /* Dummy page corresponding to discontinuity between bank1/2 */
344 stm32g4_flash_layout[1].pages_count = 1;
345 stm32g4_flash_layout[1].pages_size = BANK2_OFFSET
346 - (PAGES_PER_BANK * FLASH_PAGE_SIZE);
347 /* Bank2 */
348 stm32g4_flash_layout[2].pages_count = PAGES_PER_BANK;
349 stm32g4_flash_layout[2].pages_size = FLASH_PAGE_SIZE;
350 }
351 #else
352 static struct flash_pages_layout stm32g4_flash_layout[1];
353
354 if (stm32g4_flash_layout[0].pages_count == 0) {
355 stm32g4_flash_layout[0].pages_count = FLASH_SIZE
356 / FLASH_PAGE_SIZE;
357 stm32g4_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
358 }
359 #endif
360
361 *layout = stm32g4_flash_layout;
362 *layout_size = ARRAY_SIZE(stm32g4_flash_layout);
363 }
364
365 /* Override weak function */
flash_stm32_check_configuration(void)366 int flash_stm32_check_configuration(void)
367 {
368 #if defined(FLASH_STM32_DBANK)
369 if (READ_BIT(FLASH->OPTR, FLASH_STM32_DBANK) == 0U) {
370 /* Single bank not supported when dualbank is possible */
371 LOG_ERR("Single bank configuration not supported");
372 return -ENOTSUP;
373 }
374 #endif
375 return 0;
376 }
377
