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Searched refs:CTRLA (Results 1 – 25 of 38) sorted by relevance

12

/loramac-node-3.4.0/src/boards/mcu/saml21/hri/
Dhri_aes_l21.h235 ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; in hri_aes_set_CTRLA_SWRST_bit()
242 tmp = ((Aes *)hw)->CTRLA.reg; in hri_aes_get_CTRLA_SWRST_bit()
250 ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; in hri_aes_set_CTRLA_ENABLE_bit()
257 tmp = ((Aes *)hw)->CTRLA.reg; in hri_aes_get_CTRLA_ENABLE_bit()
266 tmp = ((Aes *)hw)->CTRLA.reg; in hri_aes_write_CTRLA_ENABLE_bit()
269 ((Aes *)hw)->CTRLA.reg = tmp; in hri_aes_write_CTRLA_ENABLE_bit()
276 ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; in hri_aes_clear_CTRLA_ENABLE_bit()
283 ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; in hri_aes_toggle_CTRLA_ENABLE_bit()
290 ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; in hri_aes_set_CTRLA_CIPHER_bit()
297 tmp = ((Aes *)hw)->CTRLA.reg; in hri_aes_get_CTRLA_CIPHER_bit()
[all …]
Dhri_sercom_l21.h418 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; in hri_sercomspi_set_CTRLA_SWRST_bit()
426 tmp = ((Sercom *)hw)->SPI.CTRLA.reg; in hri_sercomspi_get_CTRLA_SWRST_bit()
435 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; in hri_sercomspi_set_CTRLA_ENABLE_bit()
443 tmp = ((Sercom *)hw)->SPI.CTRLA.reg; in hri_sercomspi_get_CTRLA_ENABLE_bit()
453 tmp = ((Sercom *)hw)->SPI.CTRLA.reg; in hri_sercomspi_write_CTRLA_ENABLE_bit()
456 ((Sercom *)hw)->SPI.CTRLA.reg = tmp; in hri_sercomspi_write_CTRLA_ENABLE_bit()
464 ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; in hri_sercomspi_clear_CTRLA_ENABLE_bit()
472 ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; in hri_sercomspi_toggle_CTRLA_ENABLE_bit()
480 ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; in hri_sercomspi_set_CTRLA_RUNSTDBY_bit()
487 tmp = ((Sercom *)hw)->SPI.CTRLA.reg; in hri_sercomspi_get_CTRLA_RUNSTDBY_bit()
[all …]
Dhri_trng_l21.h162 ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; in hri_trng_set_CTRLA_ENABLE_bit()
169 tmp = ((Trng *)hw)->CTRLA.reg; in hri_trng_get_CTRLA_ENABLE_bit()
178 tmp = ((Trng *)hw)->CTRLA.reg; in hri_trng_write_CTRLA_ENABLE_bit()
181 ((Trng *)hw)->CTRLA.reg = tmp; in hri_trng_write_CTRLA_ENABLE_bit()
188 ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; in hri_trng_clear_CTRLA_ENABLE_bit()
195 ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; in hri_trng_toggle_CTRLA_ENABLE_bit()
202 ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; in hri_trng_set_CTRLA_RUNSTDBY_bit()
209 tmp = ((Trng *)hw)->CTRLA.reg; in hri_trng_get_CTRLA_RUNSTDBY_bit()
218 tmp = ((Trng *)hw)->CTRLA.reg; in hri_trng_write_CTRLA_RUNSTDBY_bit()
221 ((Trng *)hw)->CTRLA.reg = tmp; in hri_trng_write_CTRLA_RUNSTDBY_bit()
[all …]
Dhri_wdt_l21.h183 ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; in hri_wdt_set_CTRLA_ENABLE_bit()
191 tmp = ((Wdt *)hw)->CTRLA.reg; in hri_wdt_get_CTRLA_ENABLE_bit()
201 tmp = ((Wdt *)hw)->CTRLA.reg; in hri_wdt_write_CTRLA_ENABLE_bit()
204 ((Wdt *)hw)->CTRLA.reg = tmp; in hri_wdt_write_CTRLA_ENABLE_bit()
212 ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; in hri_wdt_clear_CTRLA_ENABLE_bit()
220 ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; in hri_wdt_toggle_CTRLA_ENABLE_bit()
228 ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; in hri_wdt_set_CTRLA_WEN_bit()
236 tmp = ((Wdt *)hw)->CTRLA.reg; in hri_wdt_get_CTRLA_WEN_bit()
246 tmp = ((Wdt *)hw)->CTRLA.reg; in hri_wdt_write_CTRLA_WEN_bit()
249 ((Wdt *)hw)->CTRLA.reg = tmp; in hri_wdt_write_CTRLA_WEN_bit()
[all …]
Dhri_tc_l21.h993 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_SWRST; in hri_tc_set_CTRLA_SWRST_bit()
1001 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; in hri_tc_get_CTRLA_SWRST_bit()
1010 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ENABLE; in hri_tc_set_CTRLA_ENABLE_bit()
1018 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; in hri_tc_get_CTRLA_ENABLE_bit()
1028 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; in hri_tc_write_CTRLA_ENABLE_bit()
1031 ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; in hri_tc_write_CTRLA_ENABLE_bit()
1039 ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ENABLE; in hri_tc_clear_CTRLA_ENABLE_bit()
1047 ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ENABLE; in hri_tc_toggle_CTRLA_ENABLE_bit()
1055 ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_RUNSTDBY; in hri_tc_set_CTRLA_RUNSTDBY_bit()
1062 tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; in hri_tc_get_CTRLA_RUNSTDBY_bit()
[all …]
Dhri_opamp_l21.h69 ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_SWRST; in hri_opamp_set_CTRLA_SWRST_bit()
76 tmp = ((Opamp *)hw)->CTRLA.reg; in hri_opamp_get_CTRLA_SWRST_bit()
84 ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_ENABLE; in hri_opamp_set_CTRLA_ENABLE_bit()
91 tmp = ((Opamp *)hw)->CTRLA.reg; in hri_opamp_get_CTRLA_ENABLE_bit()
100 tmp = ((Opamp *)hw)->CTRLA.reg; in hri_opamp_write_CTRLA_ENABLE_bit()
103 ((Opamp *)hw)->CTRLA.reg = tmp; in hri_opamp_write_CTRLA_ENABLE_bit()
110 ((Opamp *)hw)->CTRLA.reg &= ~OPAMP_CTRLA_ENABLE; in hri_opamp_clear_CTRLA_ENABLE_bit()
117 ((Opamp *)hw)->CTRLA.reg ^= OPAMP_CTRLA_ENABLE; in hri_opamp_toggle_CTRLA_ENABLE_bit()
124 ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_LPMUX; in hri_opamp_set_CTRLA_LPMUX_bit()
131 tmp = ((Opamp *)hw)->CTRLA.reg; in hri_opamp_get_CTRLA_LPMUX_bit()
[all …]
Dhri_nvmctrl_l21.h211 ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); in hri_nvmctrl_set_CTRLA_CMD_bf()
218 tmp = ((Nvmctrl *)hw)->CTRLA.reg; in hri_nvmctrl_get_CTRLA_CMD_bf()
227 tmp = ((Nvmctrl *)hw)->CTRLA.reg; in hri_nvmctrl_write_CTRLA_CMD_bf()
230 ((Nvmctrl *)hw)->CTRLA.reg = tmp; in hri_nvmctrl_write_CTRLA_CMD_bf()
237 ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); in hri_nvmctrl_clear_CTRLA_CMD_bf()
244 ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); in hri_nvmctrl_toggle_CTRLA_CMD_bf()
251 tmp = ((Nvmctrl *)hw)->CTRLA.reg; in hri_nvmctrl_read_CTRLA_CMD_bf()
259 ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); in hri_nvmctrl_set_CTRLA_CMDEX_bf()
266 tmp = ((Nvmctrl *)hw)->CTRLA.reg; in hri_nvmctrl_get_CTRLA_CMDEX_bf()
275 tmp = ((Nvmctrl *)hw)->CTRLA.reg; in hri_nvmctrl_write_CTRLA_CMDEX_bf()
[all …]
Dhri_rtc_l21.h1549 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; in hri_rtcmode2_set_CTRLA_SWRST_bit()
1557 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; in hri_rtcmode2_get_CTRLA_SWRST_bit()
1566 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; in hri_rtcmode2_set_CTRLA_ENABLE_bit()
1574 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; in hri_rtcmode2_get_CTRLA_ENABLE_bit()
1584 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; in hri_rtcmode2_write_CTRLA_ENABLE_bit()
1587 ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; in hri_rtcmode2_write_CTRLA_ENABLE_bit()
1595 ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; in hri_rtcmode2_clear_CTRLA_ENABLE_bit()
1603 ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; in hri_rtcmode2_toggle_CTRLA_ENABLE_bit()
1611 ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; in hri_rtcmode2_set_CTRLA_CLKREP_bit()
1618 tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; in hri_rtcmode2_get_CTRLA_CLKREP_bit()
[all …]
Dhri_eic_l21.h194 ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; in hri_eic_set_CTRLA_SWRST_bit()
202 tmp = ((Eic *)hw)->CTRLA.reg; in hri_eic_get_CTRLA_SWRST_bit()
211 ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; in hri_eic_set_CTRLA_ENABLE_bit()
219 tmp = ((Eic *)hw)->CTRLA.reg; in hri_eic_get_CTRLA_ENABLE_bit()
229 tmp = ((Eic *)hw)->CTRLA.reg; in hri_eic_write_CTRLA_ENABLE_bit()
232 ((Eic *)hw)->CTRLA.reg = tmp; in hri_eic_write_CTRLA_ENABLE_bit()
240 ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; in hri_eic_clear_CTRLA_ENABLE_bit()
248 ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; in hri_eic_toggle_CTRLA_ENABLE_bit()
256 ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; in hri_eic_set_CTRLA_CKSEL_bit()
263 tmp = ((Eic *)hw)->CTRLA.reg; in hri_eic_get_CTRLA_CKSEL_bit()
[all …]
Dhri_pm_l21.h164 ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; in hri_pm_set_CTRLA_IORET_bit()
171 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_IORET_bit()
180 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_write_CTRLA_IORET_bit()
183 ((Pm *)hw)->CTRLA.reg = tmp; in hri_pm_write_CTRLA_IORET_bit()
190 ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; in hri_pm_clear_CTRLA_IORET_bit()
197 ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; in hri_pm_toggle_CTRLA_IORET_bit()
204 ((Pm *)hw)->CTRLA.reg |= mask; in hri_pm_set_CTRLA_reg()
211 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_reg()
219 ((Pm *)hw)->CTRLA.reg = data; in hri_pm_write_CTRLA_reg()
226 ((Pm *)hw)->CTRLA.reg &= ~mask; in hri_pm_clear_CTRLA_reg()
[all …]
Dhri_dac_l21.h326 ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; in hri_dac_set_CTRLA_SWRST_bit()
334 tmp = ((Dac *)hw)->CTRLA.reg; in hri_dac_get_CTRLA_SWRST_bit()
343 ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; in hri_dac_set_CTRLA_ENABLE_bit()
351 tmp = ((Dac *)hw)->CTRLA.reg; in hri_dac_get_CTRLA_ENABLE_bit()
361 tmp = ((Dac *)hw)->CTRLA.reg; in hri_dac_write_CTRLA_ENABLE_bit()
364 ((Dac *)hw)->CTRLA.reg = tmp; in hri_dac_write_CTRLA_ENABLE_bit()
372 ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; in hri_dac_clear_CTRLA_ENABLE_bit()
380 ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; in hri_dac_toggle_CTRLA_ENABLE_bit()
387 ((Dac *)hw)->CTRLA.reg |= mask; in hri_dac_set_CTRLA_reg()
394 tmp = ((Dac *)hw)->CTRLA.reg; in hri_dac_get_CTRLA_reg()
[all …]
Dhri_adc_l21.h278 ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; in hri_adc_set_CTRLA_SWRST_bit()
286 tmp = ((Adc *)hw)->CTRLA.reg; in hri_adc_get_CTRLA_SWRST_bit()
295 ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; in hri_adc_set_CTRLA_ENABLE_bit()
303 tmp = ((Adc *)hw)->CTRLA.reg; in hri_adc_get_CTRLA_ENABLE_bit()
313 tmp = ((Adc *)hw)->CTRLA.reg; in hri_adc_write_CTRLA_ENABLE_bit()
316 ((Adc *)hw)->CTRLA.reg = tmp; in hri_adc_write_CTRLA_ENABLE_bit()
324 ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; in hri_adc_clear_CTRLA_ENABLE_bit()
332 ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; in hri_adc_toggle_CTRLA_ENABLE_bit()
340 ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; in hri_adc_set_CTRLA_RUNSTDBY_bit()
347 tmp = ((Adc *)hw)->CTRLA.reg; in hri_adc_get_CTRLA_RUNSTDBY_bit()
[all …]
Dhri_gclk_l21.h82 ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; in hri_gclk_set_CTRLA_SWRST_bit()
90 tmp = ((Gclk *)hw)->CTRLA.reg; in hri_gclk_get_CTRLA_SWRST_bit()
98 ((Gclk *)hw)->CTRLA.reg |= mask; in hri_gclk_set_CTRLA_reg()
105 tmp = ((Gclk *)hw)->CTRLA.reg; in hri_gclk_get_CTRLA_reg()
113 ((Gclk *)hw)->CTRLA.reg = data; in hri_gclk_write_CTRLA_reg()
120 ((Gclk *)hw)->CTRLA.reg &= ~mask; in hri_gclk_clear_CTRLA_reg()
127 ((Gclk *)hw)->CTRLA.reg ^= mask; in hri_gclk_toggle_CTRLA_reg()
133 return ((Gclk *)hw)->CTRLA.reg; in hri_gclk_read_CTRLA_reg()
Dhri_tcc_l21.h3301 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; in hri_tcc_set_CTRLA_SWRST_bit()
3309 tmp = ((Tcc *)hw)->CTRLA.reg; in hri_tcc_get_CTRLA_SWRST_bit()
3318 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; in hri_tcc_set_CTRLA_ENABLE_bit()
3326 tmp = ((Tcc *)hw)->CTRLA.reg; in hri_tcc_get_CTRLA_ENABLE_bit()
3336 tmp = ((Tcc *)hw)->CTRLA.reg; in hri_tcc_write_CTRLA_ENABLE_bit()
3339 ((Tcc *)hw)->CTRLA.reg = tmp; in hri_tcc_write_CTRLA_ENABLE_bit()
3347 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; in hri_tcc_clear_CTRLA_ENABLE_bit()
3355 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; in hri_tcc_toggle_CTRLA_ENABLE_bit()
3363 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; in hri_tcc_set_CTRLA_RUNSTDBY_bit()
3370 tmp = ((Tcc *)hw)->CTRLA.reg; in hri_tcc_get_CTRLA_RUNSTDBY_bit()
[all …]
Dhri_ac_l21.h276 ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; in hri_ac_set_CTRLA_SWRST_bit()
284 tmp = ((Ac *)hw)->CTRLA.reg; in hri_ac_get_CTRLA_SWRST_bit()
293 ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; in hri_ac_set_CTRLA_ENABLE_bit()
301 tmp = ((Ac *)hw)->CTRLA.reg; in hri_ac_get_CTRLA_ENABLE_bit()
311 tmp = ((Ac *)hw)->CTRLA.reg; in hri_ac_write_CTRLA_ENABLE_bit()
314 ((Ac *)hw)->CTRLA.reg = tmp; in hri_ac_write_CTRLA_ENABLE_bit()
322 ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; in hri_ac_clear_CTRLA_ENABLE_bit()
330 ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; in hri_ac_toggle_CTRLA_ENABLE_bit()
337 ((Ac *)hw)->CTRLA.reg |= mask; in hri_ac_set_CTRLA_reg()
344 tmp = ((Ac *)hw)->CTRLA.reg; in hri_ac_get_CTRLA_reg()
[all …]
Dhri_evsys_l21.h1183 ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; in hri_evsys_set_CTRLA_SWRST_bit()
1190 tmp = ((Evsys *)hw)->CTRLA.reg; in hri_evsys_get_CTRLA_SWRST_bit()
1198 ((Evsys *)hw)->CTRLA.reg |= mask; in hri_evsys_set_CTRLA_reg()
1205 tmp = ((Evsys *)hw)->CTRLA.reg; in hri_evsys_get_CTRLA_reg()
1213 ((Evsys *)hw)->CTRLA.reg = data; in hri_evsys_write_CTRLA_reg()
1220 ((Evsys *)hw)->CTRLA.reg &= ~mask; in hri_evsys_clear_CTRLA_reg()
1227 ((Evsys *)hw)->CTRLA.reg ^= mask; in hri_evsys_toggle_CTRLA_reg()
1233 return ((Evsys *)hw)->CTRLA.reg; in hri_evsys_read_CTRLA_reg()
Dhri_usb_l21.h2121 ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; in hri_usbhost_set_CTRLA_SWRST_bit()
2129 tmp = ((Usb *)hw)->HOST.CTRLA.reg; in hri_usbhost_get_CTRLA_SWRST_bit()
2138 ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; in hri_usbhost_set_CTRLA_ENABLE_bit()
2146 tmp = ((Usb *)hw)->HOST.CTRLA.reg; in hri_usbhost_get_CTRLA_ENABLE_bit()
2156 tmp = ((Usb *)hw)->HOST.CTRLA.reg; in hri_usbhost_write_CTRLA_ENABLE_bit()
2159 ((Usb *)hw)->HOST.CTRLA.reg = tmp; in hri_usbhost_write_CTRLA_ENABLE_bit()
2167 ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; in hri_usbhost_clear_CTRLA_ENABLE_bit()
2175 ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; in hri_usbhost_toggle_CTRLA_ENABLE_bit()
2183 ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; in hri_usbhost_set_CTRLA_RUNSTDBY_bit()
2190 tmp = ((Usb *)hw)->HOST.CTRLA.reg; in hri_usbhost_get_CTRLA_RUNSTDBY_bit()
[all …]
Dhri_tal_l21.h193 ((Tal *)hw)->CTRLA.reg |= TAL_CTRLA_SWRST; in hri_tal_set_CTRLA_SWRST_bit()
200 tmp = ((Tal *)hw)->CTRLA.reg; in hri_tal_get_CTRLA_SWRST_bit()
208 ((Tal *)hw)->CTRLA.reg |= TAL_CTRLA_ENABLE; in hri_tal_set_CTRLA_ENABLE_bit()
215 tmp = ((Tal *)hw)->CTRLA.reg; in hri_tal_get_CTRLA_ENABLE_bit()
224 tmp = ((Tal *)hw)->CTRLA.reg; in hri_tal_write_CTRLA_ENABLE_bit()
227 ((Tal *)hw)->CTRLA.reg = tmp; in hri_tal_write_CTRLA_ENABLE_bit()
234 ((Tal *)hw)->CTRLA.reg &= ~TAL_CTRLA_ENABLE; in hri_tal_clear_CTRLA_ENABLE_bit()
241 ((Tal *)hw)->CTRLA.reg ^= TAL_CTRLA_ENABLE; in hri_tal_toggle_CTRLA_ENABLE_bit()
248 ((Tal *)hw)->CTRLA.reg |= mask; in hri_tal_set_CTRLA_reg()
255 tmp = ((Tal *)hw)->CTRLA.reg; in hri_tal_get_CTRLA_reg()
[all …]
/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/
Dtrng.h157 __IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ member
Dopamp.h158 __IO OPAMP_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ member
Dtc.h747 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ member
773 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ member
797 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ member
Dsercom.h1345 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ member
1369 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ member
1389 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ member
1413 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ member
Dgclk.h236 __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ member
Dpm.h260 __IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ member
Daes.h301 __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ member

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