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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_hal_tsc.h88 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */
89 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */
90 uint32_t SpreadSpectrum; /*!< Spread spectrum activation */
91 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
92 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
93 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
94 uint32_t MaxCountValue; /*!< Max count value */
95 uint32_t IODefaultMode; /*!< IO default mode */
96 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */
97 uint32_t AcquisitionMode; /*!< Acquisition mode */
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Dstm32l0xx_hal_flash_ex.h171 uint32_t TypeErase; /*!< TypeErase: Page Erase only.
174 uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
177 uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
187 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
190 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
193 …uint32_t WRPSector; /*!< WRPSector: This bitfield specifies the sector (s) which are write…
197 …uint32_t WRPSector2; /*!< WRPSector2 : This bitfield specifies the sector(s) upper Sector31…
221 uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
225 uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
228 …uint32_t PCROPSector; /*!< PCROPSector : This bitfield specifies the sector(s) which are re…
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Dstm32l0xx_hal_dma.h65 …uint32_t Request; /*!< Specifies the request selected for the specified channel.
68 …uint32_t Direction; /*!< Specifies if the data will be transferred from memory to …
72 …uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should …
76 …uint32_t MemInc; /*!< Specifies whether the memory address register should be i…
80 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
84 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
88 …uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal…
93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
154 __IO uint32_t ErrorCode; /*!< DMA Erro…
171 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
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Dstm32l0xx_ll_dma.h86 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
111 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
116 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
121 …uint32_t Direction; /*!< Specifies if the data will be transferred from memory to per…
127 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
134 …uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address i…
140 …uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address …
146 …uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data …
152 …uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data…
158 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
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Dstm32l0xx_ll_cortex.h85 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock d…
86 #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock se…
96 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< …
107 #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */
108 #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */
109 #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */
110 #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */
111 #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */
112 #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */
113 #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */
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Dstm32l0xx_ll_tim.h118 #define TIMx_OR_RMP_SHIFT ((uint32_t)16U)
119 #define TIMx_OR_RMP_MASK ((uint32_t)0x0000FFFFU)
120 #define TIM2_OR_RMP_MASK ((uint32_t)((TIM2_OR_ETR_RMP | TIM2_OR_TI4_RMP ) << TIMx_OR_RMP_SHIFT))
121 #define TIM21_OR_RMP_MASK ((uint32_t)((TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP) << …
122 #define TIM22_OR_RMP_MASK ((uint32_t)((TIM22_OR_ETR_RMP | TIM22_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT))
124 #define TIM3_OR_RMP_MASK ((uint32_t)((TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_…
172 uint32_t CounterMode; /*!< Specifies the counter mode.
177 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
184 uint32_t ClockDivision; /*!< Specifies the clock division.
195 uint32_t OCMode; /*!< Specifies the output mode.
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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_dma.h96 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
101 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
106 …uint32_t Direction; /*!< Specifies if the data will be transferred from memory to per…
112 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
119 …uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address i…
125 …uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address …
131 …uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data …
137 …uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data…
143 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
150 uint32_t Priority; /*!< Specifies the channel priority level.
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Dstm32l1xx_hal_dma.h66 …uint32_t Direction; /*!< Specifies if the data will be transferred from memory to …
70 …uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should …
73 …uint32_t MemInc; /*!< Specifies whether the memory address register should be i…
76 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
79 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
82 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
87 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
148 …__IO uint32_t ErrorCode; /*!< DMA Error…
152 …uint32_t ChannelIndex; /*!< DMA Channe…
197 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral directio…
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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_dma.h87 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
132 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
137 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
142 …uint32_t Direction; /*!< Specifies if the data will be transferred from memory to per…
148 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
155 …uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address i…
161 …uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address …
167 …uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data …
173 …uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data…
179 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
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Dstm32l4xx_ll_fmc.h179 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
182 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
186 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
190 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
193 …uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash me…
197 …uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when ac…
201 …uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory…
206 …uint32_t WriteOperation; /*!< Enables or disables the write operation in the selecte…
209 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
213 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
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Dstm32l4xx_hal_ospi.h67 …uint32_t FifoThreshold; /* This is the threshold used byt the IP to generate the inter…
71 …uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access …
74 …uint32_t MemoryType; /* It indicates the external device type connected to the OSPI.
76 …uint32_t DeviceSize; /* It defines the size of the external device connected to the…
80 …uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip sele…
83 uint32_t FreeRunningClock; /* It enables or not the free running clock.
85 …uint32_t ClockMode; /* It indicates the level of clock when the chip select is rel…
87 …uint32_t WrapSize; /* It indicates the wrap-size corresponding the external devic…
89 uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating
92 uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order
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Dstm32l4xx_ll_sdmmc.h67 …uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is mad…
71 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
76 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
80 uint32_t BusWide; /*!< Specifies the SDMMC bus width.
83 …uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled o…
86 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
90 uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled.
102 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
107 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
110 uint32_t Response; /*!< Specifies the SDMMC response type.
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Dstm32l4xx_ll_dma2d.h82 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
87 uint32_t ColorMode; /*!< Specifies the color format of the output image.
92 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
102 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
112 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
122 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
131 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
137 …uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the outpu…
144 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
150 uint32_t LineOffset; /*!< Specifies the output line offset value.
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/loramac-node-2.7.6/src/boards/mcu/saml21/cmsis/
Dcore_cmSimd.h123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
137 uint32_t result;
143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
145 uint32_t result;
151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
153 uint32_t result;
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Dcore_cm3.h236 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
238 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
240 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
242 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
243 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
244 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
245 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
246 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
248 uint32_t w; /*!< Type used for word access */
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Dcore_sc300.h236 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
238 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
240 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
242 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
243 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
244 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
245 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
246 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
248 uint32_t w; /*!< Type used for word access */
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Dcore_cm4.h283 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
285 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
286 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
287 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
295 uint32_t w; /*!< Type used for word access */
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/loramac-node-2.7.6/src/boards/mcu/stm32/cmsis/
Dcmsis_armcc_V6.h72 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) in __get_CONTROL()
74 uint32_t result; in __get_CONTROL()
87 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) in __TZ_get_CONTROL_NS()
89 uint32_t result; in __TZ_get_CONTROL_NS()
102 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) in __set_CONTROL()
114 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) in __TZ_set_CONTROL_NS()
126 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) in __get_IPSR()
128 uint32_t result; in __get_IPSR()
141 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) in __TZ_get_IPSR_NS()
143 uint32_t result; in __TZ_get_IPSR_NS()
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Dcmsis_gcc.h80 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) in __get_CONTROL()
82 uint32_t result; in __get_CONTROL()
94 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) in __set_CONTROL()
105 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) in __get_IPSR()
107 uint32_t result; in __get_IPSR()
119 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) in __get_APSR()
121 uint32_t result; in __get_APSR()
134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) in __get_xPSR()
136 uint32_t result; in __get_xPSR()
148 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) in __get_PSP()
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Dcore_sc300.h258 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
259 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
260 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
261 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
262 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
263 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
265 uint32_t w; /*!< Type used for word access */
292 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
293 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
295 uint32_t w; /*!< Type used for word access */
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Dcore_cm3.h258 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
259 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
260 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
261 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
262 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
263 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
265 uint32_t w; /*!< Type used for word access */
292 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
293 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
295 uint32_t w; /*!< Type used for word access */
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Dcore_cm4.h312 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
313 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
314 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
315 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
316 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
317 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
318 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
319 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
321 uint32_t w; /*!< Type used for word access */
351 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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Dcore_cm7.h327 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
328 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
329 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
330 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
331 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
332 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
333 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
334 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
336 uint32_t w; /*!< Type used for word access */
366 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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/loramac-node-2.7.6/src/boards/mcu/saml21/saml21b/include/component/
Devsys.h63 uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
64 uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
65 uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
66 uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
67 uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
68 uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
69 uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
70 uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
71 uint32_t USRRDY8:1; /*!< bit: 8 Channel 8 User Ready */
72 uint32_t USRRDY9:1; /*!< bit: 9 Channel 9 User Ready */
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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/Legacy/
Dstm32l4xx_hal_can_legacy.h82 uint32_t Prescaler; /*!< Specifies the length of a time quantum.
85 uint32_t Mode; /*!< Specifies the CAN operating mode.
88 uint32_t SJW; /*!< Specifies the maximum number of time quanta
93 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
96 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
99 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
102 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
105 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
108 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
111 uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
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