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Searched refs:TIM_CCMR2_IC4PSC_Pos (Results 1 – 8 of 8) sorted by relevance

/loramac-node-2.7.6/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h5712 #define TIM_CCMR2_IC4PSC_Pos (10U) macro
5713 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
5715 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
5716 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
/loramac-node-2.7.6/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h6074 #define TIM_CCMR2_IC4PSC_Pos (10U) macro
6075 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
6077 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
6078 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
/loramac-node-2.7.6/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h6233 #define TIM_CCMR2_IC4PSC_Pos (10U) macro
6234 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
6236 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
6237 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
/loramac-node-2.7.6/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h5970 #define TIM_CCMR2_IC4PSC_Pos (10U) macro
5971 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
5973 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
5974 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
/loramac-node-2.7.6/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h5970 #define TIM_CCMR2_IC4PSC_Pos (10U) macro
5971 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
5973 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
5974 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
/loramac-node-2.7.6/src/boards/NAMote72/cmsis/
Dstm32l152xc.h6794 #define TIM_CCMR2_IC4PSC_Pos (10U) macro
6795 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
6797 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
6798 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
/loramac-node-2.7.6/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h7096 #define TIM_CCMR2_IC4PSC_Pos (10U) macro
7097 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
7099 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
7100 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
/loramac-node-2.7.6/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h14376 #define TIM_CCMR2_IC4PSC_Pos (10U) macro
14377 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
14379 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
14380 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */