Home
last modified time | relevance | path

Searched refs:TIM_CCER_CC1NP (Results 1 – 20 of 20) sorted by relevance

/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_tim.h495 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is…
1828 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config()
1829 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
2032 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity()
2060 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
Dstm32l1xx_hal_tim.h282 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T…
1021 …= TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_tim.h498 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is…
1829 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config()
1830 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
2033 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity()
2061 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
Dstm32l0xx_hal_tim.h352 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T…
1057 …= TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_ll_tim.c568 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_ENCODER_Init()
670 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_HALLSENSOR_Init()
842 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); in OC1Config()
1245 (TIM_CCER_CC1P | TIM_CCER_CC1NP), in IC1Config()
Dstm32l4xx_hal_tim.c2620 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); in HAL_TIM_Encoder_Init()
5680 tmpccer &= ~TIM_CCER_CC1NP; in TIM_OC1_SetConfig()
6190 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); in TIM_TI1_SetConfig()
6191 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); in TIM_TI1_SetConfig()
6225 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); in TIM_TI1_ConfigInputStage()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_ll_tim.c471 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_ENCODER_Init()
764 (TIM_CCER_CC1P | TIM_CCER_CC1NP), in IC1Config()
Dstm32l1xx_hal_tim.c2236 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); in HAL_TIM_Encoder_Init()
4856 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); in TIM_TI1_SetConfig()
4857 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); in TIM_TI1_SetConfig()
4891 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); in TIM_TI1_ConfigInputStage()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_ll_tim.c448 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_ENCODER_Init()
742 (TIM_CCER_CC1P | TIM_CCER_CC1NP), in IC1Config()
Dstm32l0xx_hal_tim.c2229 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); in HAL_TIM_Encoder_Init()
4652 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); in TIM_TI1_SetConfig()
4653 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); in TIM_TI1_SetConfig()
4687 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); in TIM_TI1_ConfigInputStage()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_tim.h820 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is…
2797 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config()
2798 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); in LL_TIM_IC_Config()
3001 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity()
3029 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
Dstm32l4xx_hal_tim.h487 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for T…
584 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compar…
1876 …= TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
/loramac-node-2.7.6/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h5735 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare … macro
/loramac-node-2.7.6/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h6097 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare … macro
/loramac-node-2.7.6/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h6256 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare … macro
/loramac-node-2.7.6/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h5993 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare … macro
/loramac-node-2.7.6/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h5993 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare … macro
/loramac-node-2.7.6/src/boards/NAMote72/cmsis/
Dstm32l152xc.h6817 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare … macro
/loramac-node-2.7.6/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h7119 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare … macro
/loramac-node-2.7.6/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h14441 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare … macro