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Searched refs:SET_BIT (Results 1 – 25 of 239) sorted by relevance

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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_hal_rcc_ex.h600 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRYPEN);\
615 SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
627 SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN);\
652 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
667 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
691 #define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
697 #define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
707 #define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
718 #define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
719 #define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
[all …]
Dstm32l0xx_hal_rcc.h692 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
700 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
708 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
732 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
740 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
748 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
756 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
779 #define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
780 #define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
795 #define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
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Dstm32l0xx_hal.h169 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
177 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
185 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
193 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
201 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
209 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
217 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
225 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
233 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2…
241 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
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Dstm32l0xx_ll_i2c.h409 SET_BIT(I2Cx->CR1, I2C_CR1_PE); in LL_I2C_Enable()
505 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); in LL_I2C_DisableAnalogFilter()
527 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); in LL_I2C_EnableDMAReq_TX()
560 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); in LL_I2C_EnableDMAReq_RX()
634 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); in LL_I2C_DisableClockStretching()
656 SET_BIT(I2Cx->CR1, I2C_CR1_SBC); in LL_I2C_EnableSlaveByteControl()
692 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); in LL_I2C_EnableWakeUpFromStop()
730 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); in LL_I2C_EnableGeneralCall()
808 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); in LL_I2C_EnableOwnAddress1()
864 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); in LL_I2C_EnableOwnAddress2()
[all …]
Dstm32l0xx_ll_rcc.h716 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
727 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass()
747 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
814 SET_BIT(RCC->CR, RCC_CR_HSION); in LL_RCC_HSI_Enable()
845 SET_BIT(RCC->CR, RCC_CR_HSIKERON); in LL_RCC_HSI_EnableInStopMode()
865 SET_BIT(RCC->CR, RCC_CR_HSIDIVEN); in LL_RCC_HSI_EnableDivider()
888 SET_BIT(RCC->CR, RCC_CR_HSIOUTEN); in LL_RCC_HSI_EnableOutput()
954 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); in LL_RCC_HSI48_Enable()
995 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); in LL_RCC_HSI48_EnableDivider()
1037 SET_BIT(RCC->CSR, RCC_CSR_LSEON); in LL_RCC_LSE_Enable()
[all …]
Dstm32l0xx_ll_system.h451 SET_BIT(SYSCFG->CFGR2, ConfigFastModePlus); in LL_SYSCFG_EnableFastModePlus()
514 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); in LL_SYSCFG_VREFINT_EnableADC()
534 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); in LL_SYSCFG_TEMPSENSOR_Enable()
554 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP); in LL_SYSCFG_VREFINT_EnableCOMP()
575 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); in LL_SYSCFG_VREFINT_EnableHSI48()
609 SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); in LL_SYSCFG_VREFINT_Lock()
762 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); in LL_DBGMCU_EnableDBGSleepMode()
782 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); in LL_DBGMCU_EnableDBGStopMode()
802 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in LL_DBGMCU_EnableDBGStandbyMode()
846 SET_BIT(DBGMCU->APB1FZ, Periphs); in LL_DBGMCU_APB1_GRP1_FreezePeriph()
[all …]
Dstm32l0xx_ll_bus.h243 SET_BIT(RCC->AHBENR, Periphs); in LL_AHB1_GRP1_EnableClock()
319 SET_BIT(RCC->AHBRSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
371 SET_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
459 SET_BIT(RCC->APB1ENR, Periphs); in LL_APB1_GRP1_EnableClock()
613 SET_BIT(RCC->APB1RSTR, Periphs); in LL_APB1_GRP1_ForceReset()
715 SET_BIT(RCC->APB1SMENR, Periphs); in LL_APB1_GRP1_EnableClockSleep()
805 SET_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
891 SET_BIT(RCC->APB2RSTR, Periphs); in LL_APB2_GRP1_ForceReset()
945 SET_BIT(RCC->APB2SMENR, Periphs); in LL_APB2_GRP1_EnableClockSleep()
1006 SET_BIT(RCC->IOPENR, Periphs); in LL_IOP_GRP1_EnableClock()
[all …]
Dstm32l0xx_ll_usart.h557 SET_BIT(USARTx->CR1, USART_CR1_UE); in LL_USART_Enable()
597 SET_BIT(USARTx->CR1, USART_CR1_UESM); in LL_USART_EnableInStopMode()
635 SET_BIT(USARTx->CR1, USART_CR1_RE); in LL_USART_EnableDirectionRx()
657 SET_BIT(USARTx->CR1, USART_CR1_TE); in LL_USART_EnableDirectionTx()
805 SET_BIT(USARTx->CR1, USART_CR1_MME); in LL_USART_EnableMuteMode()
989 SET_BIT(USARTx->CR2, USART_CR2_CLKEN); in LL_USART_EnableSCLKOutput()
1234 SET_BIT(USARTx->CR2, USART_CR2_ABREN); in LL_USART_EnableAutoBaudRate()
1306 SET_BIT(USARTx->CR2, USART_CR2_RTOEN); in LL_USART_EnableRxTimeout()
1398 SET_BIT(USARTx->CR3, USART_CR3_RTSE); in LL_USART_EnableRTSHWFlowCtrl()
1424 SET_BIT(USARTx->CR3, USART_CR3_CTSE); in LL_USART_EnableCTSHWFlowCtrl()
[all …]
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_rcc.h657 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
665 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
674 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
683 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
691 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
699 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
708 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
718 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \
762 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
770 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
[all …]
Dstm32l4xx_hal.h252 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STO…
257 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STO…
262 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STO…
267 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STO…
272 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STO…
277 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STO…
282 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
287 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STO…
292 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STO…
297 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STO…
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Dstm32l4xx_ll_system.h505 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); in LL_SYSCFG_EnableAnalogBooster()
546 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); in LL_SYSCFG_EnableFastModePlus()
578 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0); in LL_SYSCFG_EnableIT_FPU_IOC()
588 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1); in LL_SYSCFG_EnableIT_FPU_DZC()
598 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2); in LL_SYSCFG_EnableIT_FPU_UFC()
608 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3); in LL_SYSCFG_EnableIT_FPU_OFC()
618 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4); in LL_SYSCFG_EnableIT_FPU_IDC()
628 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5); in LL_SYSCFG_EnableIT_FPU_IXC()
846 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER); in LL_SYSCFG_EnableSRAM2Erase()
911 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); in LL_SYSCFG_ClearFlag_SP()
[all …]
Dstm32l4xx_hal_pwr_ex.h315 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
327 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
339 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
351 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
385 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
407 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
419 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
431 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
443 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
477 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
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Dstm32l4xx_ll_bus.h345 SET_BIT(RCC->AHB1ENR, Periphs); in LL_AHB1_GRP1_EnableClock()
433 SET_BIT(RCC->AHB1RSTR, Periphs); in LL_AHB1_GRP1_ForceReset()
493 SET_BIT(RCC->AHB1SMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
581 SET_BIT(RCC->AHB2ENR, Periphs); in LL_AHB2_GRP1_EnableClock()
723 SET_BIT(RCC->AHB2RSTR, Periphs); in LL_AHB2_GRP1_ForceReset()
821 SET_BIT(RCC->AHB2SMENR, Periphs); in LL_AHB2_GRP1_EnableClockStopSleep()
903 SET_BIT(RCC->AHB3ENR, Periphs); in LL_AHB3_GRP1_EnableClock()
967 SET_BIT(RCC->AHB3RSTR, Periphs); in LL_AHB3_GRP1_ForceReset()
1009 SET_BIT(RCC->AHB3SMENR, Periphs); in LL_AHB3_GRP1_EnableClockStopSleep()
1105 SET_BIT(RCC->APB1ENR1, Periphs); in LL_APB1_GRP1_EnableClock()
[all …]
Dstm32l4xx_ll_i2c.h409 SET_BIT(I2Cx->CR1, I2C_CR1_PE); in LL_I2C_Enable()
505 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); in LL_I2C_DisableAnalogFilter()
527 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); in LL_I2C_EnableDMAReq_TX()
560 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); in LL_I2C_EnableDMAReq_RX()
634 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); in LL_I2C_DisableClockStretching()
656 SET_BIT(I2Cx->CR1, I2C_CR1_SBC); in LL_I2C_EnableSlaveByteControl()
692 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); in LL_I2C_EnableWakeUpFromStop()
730 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); in LL_I2C_EnableGeneralCall()
808 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); in LL_I2C_EnableOwnAddress1()
864 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); in LL_I2C_EnableOwnAddress2()
[all …]
Dstm32l4xx_ll_dmamux.h788 …SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->… in LL_DMAMUX_EnableEventGeneration()
866 …SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->… in LL_DMAMUX_EnableSync()
1039 …SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGC… in LL_DMAMUX_EnableRequestGen()
1448 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); in LL_DMAMUX_ClearFlag_SO0()
1459 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); in LL_DMAMUX_ClearFlag_SO1()
1470 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); in LL_DMAMUX_ClearFlag_SO2()
1481 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); in LL_DMAMUX_ClearFlag_SO3()
1492 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); in LL_DMAMUX_ClearFlag_SO4()
1503 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); in LL_DMAMUX_ClearFlag_SO5()
1514 SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); in LL_DMAMUX_ClearFlag_SO6()
[all …]
Dstm32l4xx_ll_lptim.h364 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); in LL_LPTIM_Enable()
418 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); in LL_LPTIM_EnableResetAfterRead()
457 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST); in LL_LPTIM_ResetCounter()
787 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); in LL_LPTIM_EnableTimeout()
1052 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); in LL_LPTIM_EnableEncoderMode()
1094 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); in LL_LPTIM_ClearFLAG_CMPM()
1116 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); in LL_LPTIM_ClearFLAG_ARRM()
1138 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF); in LL_LPTIM_ClearFlag_EXTTRIG()
1160 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF); in LL_LPTIM_ClearFlag_CMPOK()
1182 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF); in LL_LPTIM_ClearFlag_ARROK()
[all …]
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_pwr_ex.c222 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); in HAL_PWREx_ControlVoltageScaling()
242 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); in HAL_PWREx_ControlVoltageScaling()
307 SET_BIT(PWR->CR4, PWR_CR4_VBE); in HAL_PWREx_EnableBatteryCharging()
329 SET_BIT(PWR->CR2, PWR_CR2_USV); in HAL_PWREx_EnableVddUSB()
351 SET_BIT(PWR->CR2, PWR_CR2_IOSV); in HAL_PWREx_EnableVddIO2()
372 SET_BIT(PWR->CR3, PWR_CR3_EIWF); in HAL_PWREx_EnableInternalWakeUpLine()
418 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); in HAL_PWREx_EnableGPIOPullUp()
422 SET_BIT(PWR->PUCRB, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
426 SET_BIT(PWR->PUCRC, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
431 SET_BIT(PWR->PUCRD, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
[all …]
Dstm32l4xx_hal_adc.c532 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); in HAL_ADC_Init()
535 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_Init()
696 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); in HAL_ADC_Init()
737 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); in HAL_ADC_DeInit()
748 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); in HAL_ADC_DeInit()
791 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); in HAL_ADC_DeInit()
795 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); in HAL_ADC_DeInit()
1322 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); in HAL_ADC_Start()
1456 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); in HAL_ADC_PollForConversion()
1469 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); in HAL_ADC_PollForConversion()
[all …]
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_flash_ramfunc.c191 SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); in HAL_FLASHEx_EraseParallelPage()
192 SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); in HAL_FLASHEx_EraseParallelPage()
193 SET_BIT(FLASH->PECR, FLASH_PECR_PROG); in HAL_FLASHEx_EraseParallelPage()
250 SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); in HAL_FLASHEx_ProgramParallelHalfPage()
258 SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); in HAL_FLASHEx_ProgramParallelHalfPage()
259 SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); in HAL_FLASHEx_ProgramParallelHalfPage()
260 SET_BIT(FLASH->PECR, FLASH_PECR_PROG); in HAL_FLASHEx_ProgramParallelHalfPage()
338 SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); in HAL_FLASHEx_HalfPageProgram()
346 SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); in HAL_FLASHEx_HalfPageProgram()
347 SET_BIT(FLASH->PECR, FLASH_PECR_PROG); in HAL_FLASHEx_HalfPageProgram()
[all …]
Dstm32l1xx_hal_spi.c366 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); in HAL_SPI_Transmit()
392 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); in HAL_SPI_Transmit()
399 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); in HAL_SPI_Transmit()
406 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); in HAL_SPI_Transmit()
512 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); in HAL_SPI_Receive()
533 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); in HAL_SPI_Receive()
561 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); in HAL_SPI_Receive()
581 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); in HAL_SPI_Receive()
678 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); in HAL_SPI_TransmitReceive()
708 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); in HAL_SPI_TransmitReceive()
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Dstm32l1xx_hal_adc.c512 SET_BIT(tmp_cr1, ADC_CR1_DISCEN | in HAL_ADC_Init()
521 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); in HAL_ADC_Init()
524 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_Init()
591 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_Init()
629 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); in HAL_ADC_DeInit()
869 SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART); in HAL_ADC_Start()
951 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); in HAL_ADC_PollForConversion()
971 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); in HAL_ADC_PollForConversion()
991 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); in HAL_ADC_PollForConversion()
1009 SET_BIT(hadc->State, HAL_ADC_STATE_READY); in HAL_ADC_PollForConversion()
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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_hal.h370 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
378 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
386 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
394 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
402 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
410 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
418 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
426 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
434 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
442 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS…
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Dstm32l1xx_ll_rcc.h521 SET_BIT(RCC->CR, RCC_CR_CSSON); in LL_RCC_HSE_EnableCSS()
542 SET_BIT(RCC->CR, RCC_CR_HSEBYP); in LL_RCC_HSE_EnableBypass()
562 SET_BIT(RCC->CR, RCC_CR_HSEON); in LL_RCC_HSE_Enable()
629 SET_BIT(RCC->CR, RCC_CR_HSION); in LL_RCC_HSI_Enable()
703 SET_BIT(RCC->CSR, RCC_CSR_LSEON); in LL_RCC_LSE_Enable()
723 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); in LL_RCC_LSE_EnableBypass()
744 SET_BIT(RCC->CSR, RCC_CSR_LSECSSON); in LL_RCC_LSE_EnableCSS()
797 SET_BIT(RCC->CSR, RCC_CSR_LSION); in LL_RCC_LSI_Enable()
835 SET_BIT(RCC->CR, RCC_CR_MSION); in LL_RCC_MSI_Enable()
1148 SET_BIT(RCC->CSR, RCC_CSR_RTCEN); in LL_RCC_EnableRTC()
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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_pwr.c343 SET_BIT(PWR->CR, PWR_CR_DBP); in HAL_PWR_EnableBkUpAccess()
414 SET_BIT(PWR->CR, PWR_CR_PVDE); in HAL_PWR_EnablePVD()
441 SET_BIT(PWR->CSR, WakeUpPinx); in HAL_PWR_EnableWakeUpPin()
490 SET_BIT(tmpreg, Regulator); in HAL_PWR_EnterSLEEPMode()
552 SET_BIT(tmpreg, Regulator); in HAL_PWR_EnterSTOPMode()
558 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
595 SET_BIT(PWR->CR, PWR_CR_PDDS); in HAL_PWR_EnterSTANDBYMode()
598 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTANDBYMode()
619 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
645 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
Dstm32l0xx_hal_adc.c412 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); in HAL_ADC_Init()
516 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); in HAL_ADC_Init()
519 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_Init()
599 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); in HAL_ADC_DeInit()
908 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); in HAL_ADC_PollForConversion()
933 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); in HAL_ADC_PollForConversion()
944 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); in HAL_ADC_PollForConversion()
972 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); in HAL_ADC_PollForConversion()
975 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); in HAL_ADC_PollForConversion()
1029 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); in HAL_ADC_PollForEvent()
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