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Searched refs:SCR (Results 1 – 25 of 30) sorted by relevance

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/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_pwr.c472 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode()
518 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode()
534 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode()
554 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode()
576 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
589 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
602 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
615 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_pwr.c496 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSLEEPMode()
558 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
575 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
598 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTANDBYMode()
619 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
632 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
645 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
658 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_pwr.c491 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode()
579 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode()
602 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
615 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
629 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
642 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
Dstm32l4xx_hal_pwr_ex.c1184 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP0Mode()
1201 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP0Mode()
1235 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP1Mode()
1252 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP1Mode()
1287 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP2Mode()
1304 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP2Mode()
1327 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSHUTDOWNMode()
Dstm32l4xx_hal_rtc_ex.c498 hrtc->Instance->SCR = RTC_SCR_CTSF; in HAL_RTCEx_TamperTimeStampIRQHandler()
505 tamp->SCR = tmp; in HAL_RTCEx_TamperTimeStampIRQHandler()
1012 hrtc->Instance->SCR = RTC_SCR_CWUTF;
2036 tamp->SCR = Tamper;
Dstm32l4xx_hal_rtc.c1692 hrtc->Instance->SCR = RTC_SCR_CALRAF; in HAL_RTC_AlarmIRQHandler()
1705 hrtc->Instance->SCR = RTC_SCR_CALRBF; in HAL_RTC_AlarmIRQHandler()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_cortex.h329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_cortex.h329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
Dstm32l4xx_ll_pwr.h1460 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); in LL_PWR_ClearFlag_SB()
1470 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); in LL_PWR_ClearFlag_WU()
1480 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); in LL_PWR_ClearFlag_WU5()
1490 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); in LL_PWR_ClearFlag_WU4()
1500 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); in LL_PWR_ClearFlag_WU3()
1510 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); in LL_PWR_ClearFlag_WU2()
1520 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); in LL_PWR_ClearFlag_WU1()
Dstm32l4xx_hal_pwr.h234 (PWR->SCR = (__FLAG__)) :\
235 (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
Dstm32l4xx_ll_rtc.h3593 SET_BIT(RTCx->SCR, RTC_SCR_CITSF); in LL_RTC_ClearFlag_ITS()
3604 SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF); in LL_RTC_ClearFlag_TSOV()
3615 SET_BIT(RTCx->SCR, RTC_SCR_CTSF); in LL_RTC_ClearFlag_TS()
3626 SET_BIT(RTCx->SCR, RTC_SCR_CWUTF); in LL_RTC_ClearFlag_WUT()
3637 SET_BIT(RTCx->SCR, RTC_SCR_CALRBF); in LL_RTC_ClearFlag_ALRB()
3648 SET_BIT(RTCx->SCR, RTC_SCR_CALRAF); in LL_RTC_ClearFlag_ALRA()
3859 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F); in LL_RTC_ClearFlag_TAMP1()
3870 SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F); in LL_RTC_ClearFlag_TAMP2()
Dstm32l4xx_hal_rtc.h737 …_, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? (((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRAF)…
738 … ((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRBF)))
Dstm32l4xx_hal_rtc_ex.h557 #define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = (__FLAG__))
1150 …TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (__HANDLE__)->TampOffset))->SCR) = (__FLAG__))
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_cortex.h318 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
329 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
353 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
365 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
377 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
/loramac-node-2.7.6/src/boards/mcu/saml21/hri/
Dhri_systemcontrol_l21.h960 ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPONEXIT; in hri_systemcontrol_set_SCR_SLEEPONEXIT_bit()
967 tmp = ((Systemcontrol *)hw)->SCR.reg; in hri_systemcontrol_get_SCR_SLEEPONEXIT_bit()
976 tmp = ((Systemcontrol *)hw)->SCR.reg; in hri_systemcontrol_write_SCR_SLEEPONEXIT_bit()
979 ((Systemcontrol *)hw)->SCR.reg = tmp; in hri_systemcontrol_write_SCR_SLEEPONEXIT_bit()
986 ((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPONEXIT; in hri_systemcontrol_clear_SCR_SLEEPONEXIT_bit()
993 ((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPONEXIT; in hri_systemcontrol_toggle_SCR_SLEEPONEXIT_bit()
1000 ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPDEEP; in hri_systemcontrol_set_SCR_SLEEPDEEP_bit()
1007 tmp = ((Systemcontrol *)hw)->SCR.reg; in hri_systemcontrol_get_SCR_SLEEPDEEP_bit()
1016 tmp = ((Systemcontrol *)hw)->SCR.reg; in hri_systemcontrol_write_SCR_SLEEPDEEP_bit()
1019 ((Systemcontrol *)hw)->SCR.reg = tmp; in hri_systemcontrol_write_SCR_SLEEPDEEP_bit()
[all …]
/loramac-node-2.7.6/src/boards/mcu/saml21/cmsis/
Dcore_cm0.h340 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_cm0plus.h355 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_sc000.h346 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_cm3.h354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
Dcore_sc300.h354 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register … member
/loramac-node-2.7.6/src/boards/mcu/stm32/cmsis/
Dcore_cm0.h395 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm0plus.h413 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_sc000.h401 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm3.h423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_sc300.h423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member

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