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Searched refs:RCC_CFGR_MCOSEL_PLL (Results 1 – 9 of 9) sorted by relevance

/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_rcc.h297 #define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MC…
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_rcc.h349 #define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MC…
/loramac-node-2.7.6/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h3646 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divid… macro
3673 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
/loramac-node-2.7.6/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h3918 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divid… macro
3948 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
/loramac-node-2.7.6/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h4060 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divid… macro
4090 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
/loramac-node-2.7.6/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h3938 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divid… macro
3971 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
/loramac-node-2.7.6/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h3938 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divid… macro
3971 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
/loramac-node-2.7.6/src/boards/NAMote72/cmsis/
Dstm32l152xc.h4331 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divid… macro
4364 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
/loramac-node-2.7.6/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h4401 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divid… macro
4434 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL