Searched refs:RCC_CCIPR_CLK48SEL_0 (Results 1 – 4 of 4) sorted by relevance
613 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as …633 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0651 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
548 #define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 c…566 #define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG cloc…584 #define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB cloc…
1314 case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */ in HAL_RCCEx_GetPeriphCLKFreq()1405 case RCC_CCIPR_CLK48SEL_0: /* PLLSAI1 ? */ in HAL_RCCEx_GetPeriphCLKFreq()
11583 #define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */ macro
