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Searched refs:DMA1_BASE (Results 1 – 11 of 11) sorted by relevance

/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_dma.h65 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
66 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
67 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
68 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
69 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
71 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
74 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
86 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_dma.h68 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
69 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
70 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
71 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
72 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
73 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
74 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
87 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
/loramac-node-2.7.6/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_dma.h65 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
66 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
67 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
68 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
69 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
70 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
71 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
/loramac-node-2.7.6/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h595 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) macro
596 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
597 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
598 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
599 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
600 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
601 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
602 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
603 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
662 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
/loramac-node-2.7.6/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h681 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) macro
682 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
683 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
684 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
685 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
686 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
687 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
688 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
689 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
752 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
/loramac-node-2.7.6/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h696 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) macro
697 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
698 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
699 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
700 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
701 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
702 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
703 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
704 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
768 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
/loramac-node-2.7.6/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h640 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) macro
641 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
642 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
643 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
644 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
645 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
646 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
647 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
710 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
/loramac-node-2.7.6/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h640 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) macro
641 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
642 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
643 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
644 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
645 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
646 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
647 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
710 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
/loramac-node-2.7.6/src/boards/NAMote72/cmsis/
Dstm32l152xc.h712 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) macro
713 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
714 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
715 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
716 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
717 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
718 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
719 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
795 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
/loramac-node-2.7.6/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h733 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) macro
734 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
735 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
736 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
737 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
738 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
739 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
740 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
820 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
/loramac-node-2.7.6/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h1244 #define DMA1_BASE (AHB1PERIPH_BASE) macro
1252 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
1253 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
1254 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
1255 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
1256 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1257 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1258 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
1259 #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
1407 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)