Searched refs:CHCFGR1 (Results 1 – 2 of 2) sorted by relevance
411 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); in HAL_DFSDM_ChannelInit()412 DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; in HAL_DFSDM_ChannelInit()415 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); in HAL_DFSDM_ChannelInit()420 DFSDM1_Channel0->CHCFGR1 |= (uint32_t)((hdfsdm_channel->Init.OutputClock.Divider - 1U) << in HAL_DFSDM_ChannelInit()425 DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; in HAL_DFSDM_ChannelInit()429 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | in HAL_DFSDM_ChannelInit()431 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | in HAL_DFSDM_ChannelInit()436 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); in HAL_DFSDM_ChannelInit()437 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | in HAL_DFSDM_ChannelInit()451 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; in HAL_DFSDM_ChannelInit()[all …]
395 …__IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: … member
