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Searched refs:XSHAL_STRICT_CACHEATTR_BYPASS (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dsystem.h160 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFFFF22 /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/
Dsystem.h177 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFFFF22 /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dsystem.h160 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF2222FF /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dsystem.h166 #define XSHAL_STRICT_CACHEATTR_BYPASS 0x2F2FFFF2 /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/
Dsystem.h165 #define XSHAL_STRICT_CACHEATTR_BYPASS 0x33CCCCCC /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dsystem.h177 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFF2F2FF /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/sample_controller/xtensa/config/
Dsystem.h177 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/
Dsystem.h177 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFFFF2F /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dsystem.h181 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF22FFFF /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dsystem.h181 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF22FFFF /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dsystem.h181 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF22FFFF /* disable caches in bypass mode */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dsystem.h181 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF22FFFF /* disable caches in bypass mode */ macro