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Searched refs:XCHAL_NUM_MISC_REGS (Results 1 – 13 of 13) sorted by relevance

/hal_xtensa-3.6.0/include/xtensa/
Dxtruntime-core-state.h119 #if XCHAL_NUM_MISC_REGS
120 STRUCT_AFIELD(long,4,CS_SA_,misc,XCHAL_NUM_MISC_REGS)
/hal_xtensa-3.6.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h80 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h85 #define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h85 #define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h85 #define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h85 #define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h83 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h84 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h81 #define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h84 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_imx8ulp/xtensa/config/
Dcore-isa.h83 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h81 #define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ macro
/hal_xtensa-3.6.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h81 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ macro