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Searched refs:XCHAL_HAVE_S32C1I (Results 1 – 15 of 15) sorted by relevance

/hal_xtensa-3.5.0/include/xtensa/
Dxtruntime-core-state.h88 #if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
224 #if XCHAL_HAVE_S32C1I
Dcore-macros.h429 #if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200 in XTHAL_COMPARE_AND_SET()
/hal_xtensa-3.5.0/src/hal/
Dmp_asm.S66 #elif XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
Dmisc.c66 const unsigned char Xthal_have_s32c1i = XCHAL_HAVE_S32C1I;
/hal_xtensa-3.5.0/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h76 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h81 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h81 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h81 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h81 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h79 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h77 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_imx8/xtensa/config/
Dcore-isa.h80 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h80 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h77 #define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ macro
/hal_xtensa-3.5.0/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h77 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ macro