Searched refs:RCC_PLL1CFGR3_PLL1PDIV2_Pos (Results 1 – 10 of 10) sorted by relevance
1674 …scInitStruct->PLL1.PLLP2 = ((cfgr_value & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos); in HAL_RCC_GetOscConfig()2073 …LLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos))); in RCC_PLL_Config()2231 …PLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos))) in RCC_PLL_IsNewConfig()
3191 …LLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos))); in HAL_RCCEx_PLLSSCGConfig()
316 pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos; in SystemCoreClockUpdate()
373 pllp2 = (pllcfgr & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos; in SystemCoreClockUpdate()
25392 #define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24U) macro25393 #define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x070000…
26541 #define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24U) macro26542 #define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x070000…
26299 #define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24U) macro26300 #define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x070000…
25634 #define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24U) macro25635 #define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x070000…
5238 MODIFY_REG(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2, P2 << RCC_PLL1CFGR3_PLL1PDIV2_Pos); in LL_RCC_PLL1_SetP2()5248 …eturn (uint32_t)(READ_BIT(RCC->PLL1CFGR3, RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV2_Pos); in LL_RCC_PLL1_GetP2()
3643 ((((__PLLP2__) << RCC_PLL1CFGR3_PLL1PDIV2_Pos) & RCC_PLL1CFGR3_PLL1PDIV2)))); \
