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Searched refs:LL_RCC_WriteReg (Results 1 – 25 of 49) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_rcc.c129 LL_RCC_WriteReg(CFGR, vl_mask); in LL_RCC_DeInit()
142 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
152 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
156 LL_RCC_WriteReg(CR2, 0x00000000U); in LL_RCC_DeInit()
168 LL_RCC_WriteReg(CFGR2, 0x00000000U); in LL_RCC_DeInit()
171 LL_RCC_WriteReg(CFGR3, 0x00000000U); in LL_RCC_DeInit()
183 LL_RCC_WriteReg(CIR, vl_mask); in LL_RCC_DeInit()
186 LL_RCC_WriteReg(CIR, 0x00000000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_rcc.c158 …LL_RCC_WriteReg(CFGR, 0x00070000U); /* MSI selected as System Clock and all prescaler to not divid… in LL_RCC_DeInit()
165 LL_RCC_WriteReg(CR, 0x00000061); in LL_RCC_DeInit()
172 LL_RCC_WriteReg(PLLCFGR, 0x22041000U); in LL_RCC_DeInit()
180 LL_RCC_WriteReg(PLLSAI1CFGR, 0x22041000U); in LL_RCC_DeInit()
184 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
198 LL_RCC_WriteReg(CICR, vl_mask); in LL_RCC_DeInit()
205 LL_RCC_WriteReg(SMPSCR, 0x00000301U); /* MSI default clock source */ in LL_RCC_DeInit()
217 LL_RCC_WriteReg(HSECR, HSE_CONTROL_UNLOCK_KEY); in LL_RCC_DeInit()
218 …LL_RCC_WriteReg(HSECR, LL_RCC_HSE_CURRENTMAX_3); /* HSEGMC set to default value 011, current max l… in LL_RCC_DeInit()
221 LL_RCC_WriteReg(EXTCFGR, 0x00030000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_rcc.c150 LL_RCC_WriteReg(CFGR1, 0x00000000U); in LL_RCC_DeInit()
151 LL_RCC_WriteReg(CFGR2, 0x00000000U); in LL_RCC_DeInit()
164 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
172 LL_RCC_WriteReg(PLL1CFGR, 0x0U); in LL_RCC_DeInit()
175 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U); in LL_RCC_DeInit()
178 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
188 LL_RCC_WriteReg(CICR, vl_mask); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_rcc.c98 LL_RCC_WriteReg(CFGR, vl_mask); in LL_RCC_DeInit()
105 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
114 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
117 LL_RCC_WriteReg(CIR, 0x00000000U); in LL_RCC_DeInit()
127 LL_RCC_WriteReg(CIR, vl_mask); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_ll_rcc.c135 LL_RCC_WriteReg(CFGR, vl_mask); in LL_RCC_DeInit()
146 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
155 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
161 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
175 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
178 LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_rcc.c100 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
111 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
125 LL_RCC_WriteReg(PLLCFGR, 0x24003010U); in LL_RCC_DeInit()
128 LL_RCC_WriteReg(PLLI2SCFGR, 0x20003000U); in LL_RCC_DeInit()
131 LL_RCC_WriteReg(CIR, 0x00000000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_rcc.c242 LL_RCC_WriteReg(CFGR, vl_mask); in LL_RCC_DeInit()
255 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
265 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
268 LL_RCC_WriteReg(CFGR2, 0x00000000U); in LL_RCC_DeInit()
271 LL_RCC_WriteReg(CFGR3, 0x00000000U); in LL_RCC_DeInit()
278 LL_RCC_WriteReg(CIR, vl_mask); in LL_RCC_DeInit()
281 LL_RCC_WriteReg(CIR, 0x00000000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_ll_rcc.c104 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
107 LL_RCC_WriteReg(CR, RCC_CR_HSION); in LL_RCC_DeInit()
110 LL_RCC_WriteReg(CR, RCC_CR_HSION); in LL_RCC_DeInit()
113 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
116 LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_ll_rcc.c137 …LL_RCC_WriteReg(CFGR, 0x00070000U); /* MSI selected as System Clock and all prescaler to not divid… in LL_RCC_DeInit()
147 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
154 LL_RCC_WriteReg(PLLCFGR, 0x22041000U); in LL_RCC_DeInit()
157 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
163 LL_RCC_WriteReg(CICR, vl_mask); in LL_RCC_DeInit()
169 LL_RCC_WriteReg(EXTCFGR, 0x00030000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_rcc.c199 LL_RCC_WriteReg(CFGR1, 0x00000000U); in LL_RCC_DeInit()
200 LL_RCC_WriteReg(CFGR2, 0x00000000U); in LL_RCC_DeInit()
201 LL_RCC_WriteReg(CFGR3, 0x00000000U); in LL_RCC_DeInit()
211 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
219 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U); in LL_RCC_DeInit()
222 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U); in LL_RCC_DeInit()
225 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U); in LL_RCC_DeInit()
231 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
237 LL_RCC_WriteReg(CICR, vl_mask); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_rcc.c153 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
163 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
171 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); in LL_RCC_DeInit()
174 LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos); in LL_RCC_DeInit()
177 LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos); in LL_RCC_DeInit()
183 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
188 LL_RCC_WriteReg(CICR, vl_mask); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_rcc.c157 LL_RCC_WriteReg(CFGR, LL_RCC_SYS_CLKSOURCE_HSI); in LL_RCC_DeInit()
161 LL_RCC_WriteReg(CR, RCC_CR_HSION); in LL_RCC_DeInit()
162 LL_RCC_WriteReg(CR, RCC_CR_HSION); in LL_RCC_DeInit()
169 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); in LL_RCC_DeInit()
172 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
178 LL_RCC_WriteReg(CICR, vl_mask); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_rcc.c177 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
180 LL_RCC_WriteReg(CR, RCC_CR_HSION); in LL_RCC_DeInit()
183 LL_RCC_WriteReg(CR, RCC_CR_HSION); in LL_RCC_DeInit()
190 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); in LL_RCC_DeInit()
193 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
196 LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_ll_rcc.c201 LL_RCC_WriteReg(PLLCKSELR, \ in LL_RCC_DeInit()
205 LL_RCC_WriteReg(PLLCFGR, 0U); in LL_RCC_DeInit()
208 LL_RCC_WriteReg(PLL1DIVR1, 0x01010280U); in LL_RCC_DeInit()
209 LL_RCC_WriteReg(PLL1DIVR2, 0x00000101U); in LL_RCC_DeInit()
215 LL_RCC_WriteReg(PLL2DIVR1, 0x01010280U); in LL_RCC_DeInit()
216 LL_RCC_WriteReg(PLL2DIVR2, 0x00000101U); in LL_RCC_DeInit()
222 LL_RCC_WriteReg(PLL2DIVR1, 0x01010280U); in LL_RCC_DeInit()
223 LL_RCC_WriteReg(PLL2DIVR2, 0x00000101U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_rcc.c218 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
238 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
258 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); in LL_RCC_DeInit()
262 LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos); in LL_RCC_DeInit()
267 LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos); in LL_RCC_DeInit()
274 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
288 LL_RCC_WriteReg(CICR, vl_mask); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_rcc.c196 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
216 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
226 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE); in LL_RCC_DeInit()
230 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE); in LL_RCC_DeInit()
235 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_rcc.c174 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
183 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
201 LL_RCC_WriteReg(PLLCFGR, 0x24003010U); in LL_RCC_DeInit()
204 LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U); in LL_RCC_DeInit()
207 LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_ll_rcc.c141 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
152 LL_RCC_WriteReg(CR, vl_mask); in LL_RCC_DeInit()
155 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); in LL_RCC_DeInit()
161 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_rcc.c125 LL_RCC_WriteReg(CFGR, 0x00000000U); in LL_RCC_DeInit()
145 LL_RCC_WriteReg(CFGR2, 0x00000000U); in LL_RCC_DeInit()
149 LL_RCC_WriteReg(CIR, 0x00000000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_ll_rcc.c107 LL_RCC_WriteReg(CIER, 0x00000000U); in LL_RCC_DeInit()
111 LL_RCC_WriteReg(CIFR, vl_mask); in LL_RCC_DeInit()
Dstm32wb0x_hal_rcc.c240 LL_RCC_WriteReg(CIFR, vl_mask); in HAL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_rcc.c185 LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U); in LL_RCC_DeInit()
188 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U); in LL_RCC_DeInit()
194 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U); in LL_RCC_DeInit()
200 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_rcc.c217 LL_RCC_WriteReg(CFGR1, 0x00000000U); in LL_RCC_DeInit()
218 LL_RCC_WriteReg(CFGR2, 0x00000000U); in LL_RCC_DeInit()
253 LL_RCC_WriteReg(PLL1DIVR, 0x01010280U); in LL_RCC_DeInit()
262 LL_RCC_WriteReg(PLL2DIVR, 0x01010280U); in LL_RCC_DeInit()
272 LL_RCC_WriteReg(PLL3DIVR, 0x01010280U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_rcc.h355 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) macro
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_rcc.h517 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__)) macro

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