Searched refs:FSMC_BTR2_ADDHLD_Pos (Results 1 – 13 of 13) sorted by relevance
6950 #define FSMC_BTR2_ADDHLD_Pos (4U) macro6951 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */6953 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */6954 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */6955 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */6956 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
6800 #define FSMC_BTR2_ADDHLD_Pos (4U) macro6801 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */6803 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */6804 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */6805 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */6806 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7099 #define FSMC_BTR2_ADDHLD_Pos (4U) macro7100 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */7102 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */7103 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */7104 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */7105 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7249 #define FSMC_BTR2_ADDHLD_Pos (4U) macro7250 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */7252 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */7253 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */7254 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */7255 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
6844 #define FSMC_BTR2_ADDHLD_Pos (4U) macro6845 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */6847 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */6848 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */6849 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */6850 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7026 #define FSMC_BTR2_ADDHLD_Pos (4U) macro7027 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */7029 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */7030 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */7031 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */7032 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7318 #define FSMC_BTR2_ADDHLD_Pos (4U) macro7319 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */7321 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */7322 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */7323 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */7324 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7144 #define FSMC_BTR2_ADDHLD_Pos (4U) macro7145 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */7147 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */7148 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */7149 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */7150 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
6962 #define FSMC_BTR2_ADDHLD_Pos (4U) macro6963 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */6965 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */6966 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */6967 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */6968 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
6956 #define FSMC_BTR2_ADDHLD_Pos (4U) macro6957 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */6959 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */6960 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */6961 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */6962 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
6958 #define FSMC_BTR2_ADDHLD_Pos (4U) macro6959 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */6961 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */6962 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */6963 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */6964 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7282 #define FSMC_BTR2_ADDHLD_Pos (4U) macro7283 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */7285 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */7286 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */7287 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */7288 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7323 #define FSMC_BTR2_ADDHLD_Pos (4U) macro7324 #define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */7326 #define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */7327 #define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */7328 #define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */7329 #define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
