Searched refs:DMA_IFCR_CTEIF1_Pos (Results 1 – 25 of 160) sorted by relevance
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2926 #define DMA_IFCR_CTEIF1_Pos (3U) macro2927 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
2988 #define DMA_IFCR_CTEIF1_Pos (3U) macro2989 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3140 #define DMA_IFCR_CTEIF1_Pos (3U) macro3141 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
2975 #define DMA_IFCR_CTEIF1_Pos (3U) macro2976 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3487 #define DMA_IFCR_CTEIF1_Pos (3U) macro3488 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3459 #define DMA_IFCR_CTEIF1_Pos (3U) macro3460 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3383 #define DMA_IFCR_CTEIF1_Pos (3U) macro3384 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1031 #define DMA_IFCR_CTEIF1_Pos (3U) macro1032 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1053 #define DMA_IFCR_CTEIF1_Pos (3U) macro1054 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1076 #define DMA_IFCR_CTEIF1_Pos (3U) macro1077 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1047 #define DMA_IFCR_CTEIF1_Pos (3U) macro1048 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1072 #define DMA_IFCR_CTEIF1_Pos (3U) macro1073 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1046 #define DMA_IFCR_CTEIF1_Pos (3U) macro1047 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1108 #define DMA_IFCR_CTEIF1_Pos (3U) macro1109 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1313 #define DMA_IFCR_CTEIF1_Pos (3U) macro1314 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1084 #define DMA_IFCR_CTEIF1_Pos (3U) macro1085 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1149 #define DMA_IFCR_CTEIF1_Pos (3U) macro1150 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1277 #define DMA_IFCR_CTEIF1_Pos (3U) macro1278 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1185 #define DMA_IFCR_CTEIF1_Pos (3U) macro1186 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1226 #define DMA_IFCR_CTEIF1_Pos (3U) macro1227 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1068 #define DMA_IFCR_CTEIF1_Pos (3U) macro1069 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1074 #define DMA_IFCR_CTEIF1_Pos (3U) macro1075 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1385 #define DMA_IFCR_CTEIF1_Pos (3U) macro1386 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1257 #define DMA_IFCR_CTEIF1_Pos (3U) macro1258 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
