Searched refs:COMP_CSR_COMP2INNSEL_Pos (Results 1 – 15 of 15) sorted by relevance
1053 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1054 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1056 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1057 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1058 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
916 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro917 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */919 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */920 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */921 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1044 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1045 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1047 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1048 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1049 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
925 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro926 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */928 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */929 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */930 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
960 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro961 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */963 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */964 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */965 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1110 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1111 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1113 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1114 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1115 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
982 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro983 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */985 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */986 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */987 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1069 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1070 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1072 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1073 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1074 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1197 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1198 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1200 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1201 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1202 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1091 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1092 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1094 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1095 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1096 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1096 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1097 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1099 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1100 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1101 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1118 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1119 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1121 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1122 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1123 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1246 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1247 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1249 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1250 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1251 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1219 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1220 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1222 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1223 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1224 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1224 #define COMP_CSR_COMP2INNSEL_Pos (4U) macro1225 #define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */1227 #define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */1228 #define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */1229 #define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
