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Searched refs:PWR_CR2_SRAM3PDS1_Pos (Results 1 – 11 of 11) sorted by relevance

/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_pwr_ex.c1805 CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); in HAL_PWREx_EnableRAMsContentStopRetention()
2055 SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); in HAL_PWREx_DisableRAMsContentStopRetention()
/hal_stm32-3.6.0/stm32cube/stm32u5xx/soc/
Dstm32u575xx.h13564 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
13565 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u5f7xx.h15867 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
15868 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u595xx.h14366 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
14367 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u5a5xx.h14928 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
14929 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u585xx.h14126 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
14127 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u599xx.h18085 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
18086 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u5g7xx.h16429 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
16430 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u5a9xx.h18647 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
18648 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u5f9xx.h18993 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
18994 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…
Dstm32u5g9xx.h19555 #define PWR_CR2_SRAM3PDS1_Pos (16U) macro
19556 #define PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) /*!< 0x00010000…