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Searched refs:FSMC_PCR3_TCLR_Pos (Results 1 – 9 of 9) sorted by relevance

/hal_stm32-3.6.0/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_fsmc.c518 ((Init->TCLRSetupTime) << FSMC_PCR3_TCLR_Pos) | in FSMC_NAND_Init()
529 ((Init->TCLRSetupTime) << FSMC_PCR3_TCLR_Pos) | in FSMC_NAND_Init()
/hal_stm32-3.6.0/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h7249 #define FSMC_PCR3_TCLR_Pos (9U) macro
7250 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7252 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7253 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7254 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7255 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
Dstm32f407xx.h7549 #define FSMC_PCR3_TCLR_Pos (9U) macro
7550 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7552 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7553 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7554 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7555 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
Dstm32f415xx.h7431 #define FSMC_PCR3_TCLR_Pos (9U) macro
7432 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7434 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7435 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7436 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7437 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
Dstm32f417xx.h7728 #define FSMC_PCR3_TCLR_Pos (9U) macro
7729 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7731 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7732 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7733 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7734 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
/hal_stm32-3.6.0/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h7355 #define FSMC_PCR3_TCLR_Pos (9U) macro
7356 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7358 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7359 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7360 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7361 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
Dstm32f205xx.h7205 #define FSMC_PCR3_TCLR_Pos (9U) macro
7206 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7208 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7209 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7210 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7211 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
Dstm32f217xx.h7654 #define FSMC_PCR3_TCLR_Pos (9U) macro
7655 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7657 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7658 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7659 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7660 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
Dstm32f207xx.h7504 #define FSMC_PCR3_TCLR_Pos (9U) macro
7505 #define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7507 #define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7508 #define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7509 #define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7510 #define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */