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Searched refs:RCC_DCKCFGR1_PLLSAIDIVR_Pos (Results 1 – 11 of 11) sorted by relevance

/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_rcc_ex.c712 …>PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos); in HAL_RCCEx_GetPeriphCLKConfig()
/hal_stm32-3.5.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_rcc.h1590 …ICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos])))
/hal_stm32-3.5.0/stm32cube/stm32f7xx/soc/
Dstm32f745xx.h11023 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
11024 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11026 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11027 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
Dstm32f746xx.h11371 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
11372 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11374 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11375 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
Dstm32f750xx.h11664 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
11665 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11667 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11668 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
Dstm32f756xx.h11664 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
11665 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11667 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11668 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
Dstm32f765xx.h11578 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
11579 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11581 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11582 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
Dstm32f767xx.h11972 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
11973 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
11975 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
11976 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
Dstm32f777xx.h12265 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
12266 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
12268 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
12269 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
Dstm32f779xx.h12357 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
12358 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
12360 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
12361 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */
Dstm32f769xx.h12064 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) macro
12065 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00030000 */
12067 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00010000 */
12068 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos) /*!< 0x00020000 */