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Searched refs:DIVR (Results 1 – 5 of 5) sorted by relevance

/hal_stm32-3.5.0/lib/stm32wb/hci/
Dapp_conf.h526 #define CFG_RTC_SYNCH_PRESCALER (DIVR( LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER+1) ) - 1 )
531 #define CFG_TS_TICK_VAL DIVR( (CFG_RTCCLK_DIV * 1000000), LSE_VALUE )
532 #define CFG_TS_TICK_VAL_PS DIVR( ((uint64_t)CFG_RTCCLK_DIV * 1e12), (uint64_t)LSE_VALUE )
Dutilities_common.h109 #undef DIVR
110 #define DIVR( x, y ) (((x)+((y)/2))/(y)) macro
Dstm32_wpan_common.h122 #undef DIVR
123 #define DIVR( x, y ) (((x)+((y)/2))/(y)) macro
Dapp_common.h90 #define DIVR( x, y ) (((x)+((y)/2))/(y)) macro
/hal_stm32-3.5.0/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_rcc.h4416 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t DIVR) in LL_RCC_PLL2_SetR() argument
4418 MODIFY_REG(RCC->PLL2CFGR2, RCC_PLL2CFGR2_DIVR, (DIVR - 1U) << RCC_PLL2CFGR2_DIVR_Pos); in LL_RCC_PLL2_SetR()
4813 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t DIVR) in LL_RCC_PLL3_SetR() argument
4815 MODIFY_REG(RCC->PLL3CFGR2, RCC_PLL3CFGR2_DIVR, (DIVR - 1U) << RCC_PLL3CFGR2_DIVR_Pos); in LL_RCC_PLL3_SetR()
5210 __STATIC_INLINE void LL_RCC_PLL4_SetR(uint32_t DIVR) in LL_RCC_PLL4_SetR() argument
5212 MODIFY_REG(RCC->PLL4CFGR2, RCC_PLL4CFGR2_DIVR, (DIVR - 1U) << RCC_PLL4CFGR2_DIVR_Pos); in LL_RCC_PLL4_SetR()