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Searched refs:RCC_APB1ENR_USART2EN (Results 1 – 25 of 139) sorted by relevance

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/hal_stm32-3.4.0/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc_ex.h704 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
714 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
724 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U)
733 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U)
747 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
753 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
759 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) != 0U)
764 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN) == 0U)
781 #define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
796 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
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Dstm32l0xx_ll_bus.h112 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */
/hal_stm32-3.4.0/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc.h418 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
420 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
451 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
475 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
476 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Dstm32f1xx_ll_bus.h160 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
/hal_stm32-3.4.0/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc.h491 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
493 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
521 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
539 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
547 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Dstm32f4xx_ll_bus.h226 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
/hal_stm32-3.4.0/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc.h795 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
797 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
832 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
935 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
944 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Dstm32f3xx_ll_bus.h148 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
/hal_stm32-3.4.0/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc_ex.h1012 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1014 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1018 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
1545 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
1546 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Dstm32f0xx_ll_bus.h117 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
/hal_stm32-3.4.0/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h772 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
774 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
835 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
1150 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0U)
1165 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0U)
Dstm32l1xx_ll_bus.h126 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
/hal_stm32-3.4.0/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h742 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
744 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
830 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
864 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))!= RESET)
888 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))== RESET)
Dstm32f2xx_ll_bus.h144 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
/hal_stm32-3.4.0/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1038 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1040 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
1181 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
1588 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
1615 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Dstm32f7xx_ll_bus.h164 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
/hal_stm32-3.4.0/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h1169 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock e… macro
Dstm32f101xb.h1202 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock e… macro
/hal_stm32-3.4.0/stm32cube/stm32f0xx/soc/
Dstm32f030x8.h3160 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock en… macro
Dstm32f070x6.h3187 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock en… macro
Dstm32f030xc.h3453 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock en… macro
Dstm32f070xb.h3312 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock en… macro
/hal_stm32-3.4.0/stm32cube/stm32l0xx/soc/
Dstm32l010xb.h3523 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock en… macro
Dstm32l010x6.h3494 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock en… macro
Dstm32l010x4.h3465 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock en… macro

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