Home
last modified time | relevance | path

Searched refs:_DMA_CH_CTRL_SOURCESEL_TIMER2 (Results 1 – 25 of 35) sorted by relevance

12

/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg_dma.h879 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
890 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32hg321f32.h1231 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
1241 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32hg321f64.h1231 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
1241 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32hg108f32.h1272 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
1281 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32hg108f64.h1272 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
1281 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32hg308f32.h1284 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
1293 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32hg308f64.h1284 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
1293 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32WG/Include/
Defm32wg_dma.h1605 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
1625 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg360f128.h2034 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2053 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg360f256.h2034 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2053 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg360f64.h2034 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2053 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg230f128.h2097 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2114 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg230f256.h2097 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2114 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg230f64.h2097 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2114 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg232f128.h2097 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2114 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg232f256.h2097 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2114 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg232f64.h2097 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2114 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg330f128.h2110 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2127 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg330f256.h2110 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2127 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg330f64.h2110 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2127 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg332f128.h2110 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2127 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg332f256.h2110 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2127 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg332f64.h2110 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2127 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg840f128.h2102 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2119 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …
Defm32wg840f256.h2102 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL … macro
2119 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) …

12