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Searched refs:_EMU_DCDCMISCCTRL_LNFORCECCM_MASK (Results 1 – 25 of 72) sorted by relevance

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/hal_silabs-3.5.0/gecko/emlib/src/
Dem_emu.c2693 | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) in EMU_DCDCInit()
3137 if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) in EMU_DCDCOptimizeSlice()
3146 } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) == 0U) in EMU_DCDCOptimizeSlice()
3155 } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) in EMU_DCDCOptimizeSlice()
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG1P/Include/
Defr32fg1p_emu.h744 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b_emu.h744 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_emu.h847 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_emu.h847 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_emu.h830 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_emu.h847 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_emu.h830 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_emu.h958 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b390f1024gl112.h3034 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b390f512gl112.h3034 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b110f1024iq64.h3865 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b510f1024gl120.h3873 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b510f1024gm64.h3873 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b510f1024gl112.h3873 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b530f512im64.h3873 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b530f512iq64.h3873 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b130f512gm64.h3865 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b130f512gq64.h3865 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b130f512im64.h3865 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b130f512iq64.h3865 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b530f512iq100.h3873 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b110f1024gm64.h3865 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
Defm32gg12b110f1024gq64.h3865 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_emu.h966 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL … macro

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