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Searched refs:mask (Results 1 – 23 of 23) sorted by relevance

/hal_rpi_pico-latest/src/rp2_common/hardware_gpio/include/hardware/
Dgpio.h908 static inline void gpio_set_mask(uint32_t mask) { in gpio_set_mask() argument
910 gpioc_lo_out_set(mask); in gpio_set_mask()
912 sio_hw->gpio_set = mask; in gpio_set_mask()
921 static inline void gpio_set_mask64(uint64_t mask) { in gpio_set_mask64() argument
923 gpioc_hilo_out_set(mask); in gpio_set_mask64()
925 sio_hw->gpio_set = (uint32_t)mask; in gpio_set_mask64()
927 sio_hw->gpio_set = (uint32_t)mask; in gpio_set_mask64()
928 sio_hw->gpio_hi_set = (uint32_t)(mask >> 32u); in gpio_set_mask64()
938 static inline void gpio_set_mask_n(uint n, uint32_t mask) { in gpio_set_mask_n() argument
940 gpio_set_mask(mask); in gpio_set_mask_n()
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Dgpio_coproc.h299 __force_inline static void gpioc_index_out_xor(uint reg_index, uint32_t mask) { in gpioc_index_out_xor() argument
300 pico_default_asm_volatile ("mcrr p0, #9, %1, %0, c0" : : "r" (reg_index), "r" (mask)); in gpioc_index_out_xor()
312 __force_inline static void gpioc_index_out_set(uint reg_index, uint32_t mask) { in gpioc_index_out_set() argument
313 pico_default_asm_volatile ("mcrr p0, #10, %1, %0, c0" : : "r" (reg_index), "r" (mask)); in gpioc_index_out_set()
325 __force_inline static void gpioc_index_out_clr(uint reg_index, uint32_t mask) { in gpioc_index_out_clr() argument
326 pico_default_asm_volatile ("mcrr p0, #11, %1, %0, c0" : : "r" (reg_index), "r" (mask)); in gpioc_index_out_clr()
351 __force_inline static void gpioc_index_oe_xor(uint reg_index, uint32_t mask) { in gpioc_index_oe_xor() argument
352 pico_default_asm_volatile ("mcrr p0, #9, %1, %0, c4" : : "r" (reg_index), "r" (mask)); in gpioc_index_oe_xor()
364 __force_inline static void gpioc_index_oe_set(uint reg_index, uint32_t mask) { in gpioc_index_oe_set() argument
365 pico_default_asm_volatile ("mcrr p0, #10, %1, %0, c4" : : "r" (reg_index), "r" (mask)); in gpioc_index_oe_set()
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/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/
Darmv8m_pmu.h179 __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
180 __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
186 __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
188 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
189 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
191 __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
242 __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) in ARM_PMU_CNTR_Enable() argument
244 PMU->CNTENSET = mask; in ARM_PMU_CNTR_Enable()
254 __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) in ARM_PMU_CNTR_Disable() argument
256 PMU->CNTENCLR = mask; in ARM_PMU_CNTR_Disable()
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Darmv8m_mpu.h261 const uint32_t mask = 0xFFU << pos; in ARM_MPU_SetMemAttrEx() local
267 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); in ARM_MPU_SetMemAttrEx()
Dcmsis_iccarm_m.h591 uint32_t mask = 0x80000000U; in __CLZ() local
593 while ((data & mask) == 0U) in __CLZ()
596 mask = mask >> 1U; in __CLZ()
/hal_rpi_pico-latest/src/host/hardware_gpio/
Dgpio.c93 void gpio_set_mask(uint32_t mask) { in gpio_set_mask() argument
97 void gpio_clr_mask(uint32_t mask) { in gpio_clr_mask() argument
101 void gpio_xor_mask(uint32_t mask) { in gpio_xor_mask() argument
105 void gpio_put_masked(uint32_t mask, uint32_t value) { in gpio_put_masked() argument
117 void gpio_set_dir_out_masked(uint32_t mask) { in gpio_set_dir_out_masked() argument
121 void gpio_set_dir_in_masked(uint32_t mask) { in gpio_set_dir_in_masked() argument
125 void gpio_set_dir_masked(uint32_t mask, uint32_t value) { in gpio_set_dir_masked() argument
/hal_rpi_pico-latest/src/rp2_common/hardware_resets/include/hardware/
Dresets.h71 static __force_inline void reset_block_reg_mask(io_rw_32 *reset, uint32_t mask) { in reset_block_reg_mask() argument
72 hw_set_bits(reset, mask); in reset_block_reg_mask()
75 static __force_inline void unreset_block_reg_mask(io_rw_32 *reset, uint32_t mask) { in unreset_block_reg_mask() argument
76 hw_clear_bits(reset, mask); in unreset_block_reg_mask()
79 …e void unreset_block_reg_mask_wait_blocking(io_rw_32 *reset, io_ro_32 *reset_done, uint32_t mask) { in unreset_block_reg_mask_wait_blocking() argument
80 hw_clear_bits(reset, mask); in unreset_block_reg_mask_wait_blocking()
81 while (~*reset_done & mask) in unreset_block_reg_mask_wait_blocking()
/hal_rpi_pico-latest/src/rp2_common/hardware_dma/
Ddma.c28 void dma_claim_mask(uint32_t mask) { in dma_claim_mask() argument
29 for(uint i = 0; mask; i++, mask >>= 1u) { in dma_claim_mask()
30 if (mask & 1u) dma_channel_claim(i); in dma_claim_mask()
39 void dma_unclaim_mask(uint32_t mask) { in dma_unclaim_mask() argument
40 for(uint i = 0; mask; i++, mask >>= 1u) { in dma_unclaim_mask()
41 if (mask & 1u) dma_channel_unclaim(i); in dma_unclaim_mask()
/hal_rpi_pico-latest/src/host/hardware_gpio/include/hardware/
Dgpio.h104 void gpio_set_mask(uint32_t mask);
106 void gpio_clr_mask(uint32_t mask);
109 void gpio_xor_mask(uint32_t mask);
116 void gpio_put_masked(uint32_t mask, uint32_t value);
130 void gpio_set_dir_out_masked(uint32_t mask);
133 void gpio_set_dir_in_masked(uint32_t mask);
139 void gpio_set_dir_masked(uint32_t mask, uint32_t value);
/hal_rpi_pico-latest/src/rp2_common/hardware_base/include/hardware/
Daddress_mapped.h135 __force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { in hw_set_bits() argument
136 *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask; in hw_set_bits()
145 __force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { in hw_clear_bits() argument
146 *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask; in hw_clear_bits()
155 __force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { in hw_xor_bits() argument
156 *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; in hw_xor_bits()
/hal_rpi_pico-latest/src/rp2_common/hardware_sync/
Dsync.c31 void spin_lock_claim_mask(uint32_t mask) { in spin_lock_claim_mask() argument
32 for(uint i = 0; mask; i++, mask >>= 1u) { in spin_lock_claim_mask()
33 if (mask & 1u) spin_lock_claim(i); in spin_lock_claim_mask()
/hal_rpi_pico-latest/src/rp2_common/hardware_pio/include/hardware/
Dpio.h305 static inline void check_sm_mask(__unused uint mask) { in check_sm_mask() argument
306 valid_params_if(HARDWARE_PIO, mask < (1u << NUM_PIO_STATE_MACHINES)); in check_sm_mask()
1028 static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) { in pio_set_sm_mask_enabled() argument
1030 check_sm_mask(mask); in pio_set_sm_mask_enabled()
1031 pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u); in pio_set_sm_mask_enabled()
1050 static inline void pio_set_sm_multi_mask_enabled(PIO pio, uint32_t mask_prev, uint32_t mask, uint32… in pio_set_sm_multi_mask_enabled() argument
1052 check_sm_mask(mask); in pio_set_sm_multi_mask_enabled()
1053 pio->ctrl = (pio->ctrl & ~(mask << PIO_CTRL_SM_ENABLE_LSB)) | in pio_set_sm_multi_mask_enabled()
1054 (enabled ? ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) : 0) | in pio_set_sm_multi_mask_enabled()
1086 static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) { in pio_restart_sm_mask() argument
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/hal_rpi_pico-latest/src/rp2_common/hardware_irq/
Dirq.c78 static inline void irq_set_mask_n_enabled_internal(uint n, uint32_t mask, bool enabled) { in irq_set_mask_n_enabled_internal() argument
82 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
83 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
84 hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
85 hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
87 hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
88 hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
93 nvic_hw->icpr = mask; in irq_set_mask_n_enabled_internal()
94 nvic_hw->iser = mask; in irq_set_mask_n_enabled_internal()
96 nvic_hw->icer = mask; in irq_set_mask_n_enabled_internal()
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/hal_rpi_pico-latest/src/rp2_common/hardware_rcp/include/hardware/
Drcp.h197 static __rcpinline void rcp_bxorvalid(uint32_t b, uint32_t mask) { in rcp_bxorvalid() argument
198 rcp_asm ("mcrr p7, #3, %0, %1, c8\n" : : "r" (b), "r" (mask)); in rcp_bxorvalid()
201 static __rcpinline void rcp_bxorvalid_nodelay(uint32_t b, uint32_t mask) { in rcp_bxorvalid_nodelay() argument
202 rcp_asm ("mcrr2 p7, #3, %0, %1, c8\n" : : "r" (b), "r" (mask)); in rcp_bxorvalid_nodelay()
206 static __rcpinline void rcp_bxortrue(uint32_t b, uint32_t mask) { in rcp_bxortrue() argument
207 rcp_asm ("mcrr p7, #4, %0, %1, c0\n" : : "r" (b), "r" (mask)); in rcp_bxortrue()
210 static __rcpinline void rcp_bxortrue_nodelay(uint32_t b, uint32_t mask) { in rcp_bxortrue_nodelay() argument
211 rcp_asm ("mcrr2 p7, #4, %0, %1, c0\n" : : "r" (b), "r" (mask)); in rcp_bxortrue_nodelay()
215 static __rcpinline void rcp_bxorfalse(uint32_t b, uint32_t mask) { in rcp_bxorfalse() argument
216 rcp_asm ("mcrr p7, #5, %0, %1, c8\n" : : "r" (b), "r" (mask)); in rcp_bxorfalse()
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/hal_rpi_pico-latest/src/host/hardware_irq/include/hardware/
Dirq.h185 void irq_set_mask_enabled(uint32_t mask, bool enabled);
194 void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled);
/hal_rpi_pico-latest/src/rp2_common/hardware_irq/include/hardware/
Dirq.h268 void irq_set_mask_enabled(uint32_t mask, bool enabled);
277 void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled);
/hal_rpi_pico-latest/src/host/hardware_irq/
Dirq.c35 void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_mask_enabled)(uint32_t mask, bool enabled) { in PICO_WEAK_FUNCTION_DEF()
40 void PICO_WEAK_FUNCTION_IMPL_NAME(irq_set_mask_n_enabled)(uint n, uint32_t mask, bool enabled) { in PICO_WEAK_FUNCTION_DEF()
/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/
Dmpu_armv8.h192 const uint32_t mask = 0xFFU << pos; in ARM_MPU_SetMemAttrEx() local
198 mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); in ARM_MPU_SetMemAttrEx()
Dcmsis_iccarm.h563 uint32_t mask = 0x80000000U; in __CLZ() local
565 while ((data & mask) == 0U) in __CLZ()
568 mask = mask >> 1U; in __CLZ()
/hal_rpi_pico-latest/src/host/hardware_sync/
Dsync_core0_only.c125 void PICO_WEAK_FUNCTION_IMPL_NAME(spin_lock_claim_mask)(uint32_t mask) { in PICO_WEAK_FUNCTION_DEF()
/hal_rpi_pico-latest/src/rp2_common/hardware_flash/
Dflash.c298 static void flash_devinfo_update_field(uint16_t wdata, uint16_t mask) { in flash_devinfo_update_field() argument
302 *hw_xor_alias(devinfo) = (*devinfo ^ wdata) & mask; in flash_devinfo_update_field()
/hal_rpi_pico-latest/src/rp2_common/hardware_pwm/include/hardware/
Dpwm.h556 static inline void pwm_set_mask_enabled(uint32_t mask) { in pwm_set_mask_enabled() argument
557 pwm_hw->en = mask; in pwm_set_mask_enabled()
/hal_rpi_pico-latest/src/rp2_common/pico_bootrom/include/pico/
Dbootrom.h158 typedef void *(*rom_table_lookup_fn)(uint32_t code, uint32_t mask);