Searched refs:irq_ctrl_base (Results 1 – 2 of 2) sorted by relevance
156 …io_bank0_irq_ctrl_hw_t *irq_ctrl_base = core ? &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_… in gpio_default_irq_handler() local158 uint32_t events8 = irq_ctrl_base->ints[gpio >> 3u]; in gpio_default_irq_handler()173 …_set_irq_enabled(uint gpio, uint32_t events, bool enabled, io_bank0_irq_ctrl_hw_t *irq_ctrl_base) { in _gpio_set_irq_enabled() argument177 io_rw_32 *en_reg = &irq_ctrl_base->inte[gpio / 8]; in _gpio_set_irq_enabled()201 io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? in gpio_set_irq_enabled() local203 _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base); in gpio_set_irq_enabled()260 io_bank0_irq_ctrl_hw_t *irq_ctrl_base = &io_bank0_hw->dormant_wake_irq_ctrl; in gpio_set_dormant_irq_enabled() local261 _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base); in gpio_set_dormant_irq_enabled()
548 io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ? in gpio_get_irq_event_mask() local550 io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio >> 3u]; in gpio_get_irq_event_mask()
