Searched refs:SCB (Results 1 – 8 of 8) sorted by relevance
58 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()62 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()65 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()81 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()82 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_DisableICache()98 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()123 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()146 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()148 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()151 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()[all …]
194 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()206 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
204 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()216 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
654 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro875 …SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)))… in __NVIC_SetPriority()899 …return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - _… in __NVIC_GetPriority()969 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); in __NVIC_SetVector()990 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); in __NVIC_GetVector()1007 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
196 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()208 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
135 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()147 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
2049 …#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration stru… macro2332 …reg_value = SCB->AIRCR; /* read old register c… in __NVIC_SetPriorityGrouping()2337 SCB->AIRCR = reg_value; in __NVIC_SetPriorityGrouping()2348 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); in __NVIC_GetPriorityGrouping()2563 …SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uin… in __NVIC_SetPriority()2586 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); in __NVIC_GetPriority()2654 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); in __NVIC_SetVector()2670 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); in __NVIC_GetVector()2683 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()2684 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in __NVIC_SystemReset()
31 SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; in main()
