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Searched refs:XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL (Results 1 – 11 of 11) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/cfgs_rv32m1/
Dfsl_xcvr_gfsk_bt_0p7_h_0p5_config.c142 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
146 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
271 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
275 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
398 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
402 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
526 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
530 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
Dfsl_xcvr_msk_config.c132 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x11),
136 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x11),
261 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x12),
265 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x12),
391 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x13),
395 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x13),
520 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x14),
524 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x14),
Dfsl_xcvr_gfsk_bt_0p5_h_0p5_config.c129 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
133 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
260 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
264 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
391 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
395 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
521 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
525 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
Dfsl_xcvr_gfsk_bt_0p3_h_0p5_config.c148 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
151 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
268 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
271 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
394 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
397 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
520 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
523 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
Dfsl_xcvr_gfsk_bt_0p5_h_0p32_config.c129 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
132 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
256 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
259 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
382 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
385 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
508 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
511 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
Dfsl_xcvr_gfsk_bt_0p5_h_1p0_config.c130 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
134 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
259 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
263 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
387 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
391 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
Dfsl_xcvr_gfsk_bt_0p5_h_0p7_config.c130 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
134 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
258 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
262 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
386 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
390 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
Dfsl_xcvr_ble_config.c134 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
137 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x25),
Dfsl_xcvr_ant_config.c183 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
186 XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(0x10),
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h26551 #define XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_M… macro
DRV32M1_zero_riscy.h25707 #define XCVR_PHY_PHY_FSK_MISC_EL_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_FSK_M… macro