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Searched refs:SCG_ROSCCSR_ROSCERR_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.h1424 return (bool)(SCG->ROSCCSR & SCG_ROSCCSR_ROSCERR_MASK); in CLOCK_IsRtcOscErr()
1432 SCG->ROSCCSR |= SCG_ROSCCSR_ROSCERR_MASK; in CLOCK_ClearRtcOscErr()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17086 #define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) macro
17092 … (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK)
DRV32M1_zero_riscy.h17914 #define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) macro
17920 … (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK)