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Searched refs:RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h15070 #define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK (0x10000000U) macro
15072 …(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK)
DRV32M1_zero_riscy.h15898 #define RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK (0x10000000U) macro
15900 …(((uint32_t)(x)) << RSIM_SW_CONFIG_BLOCK_SOC_RESETS_SHIFT)) & RSIM_SW_CONFIG_BLOCK_SOC_RESETS_MASK)