| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/SupportFunctions/ |
| D | arm_bitonic_sort_f32.c | 210 float32x4x2_t out1 = vzipq_f32(a.val[0], b.val[0]); in arm_bitonic_resort_16_f32()
211 float32x4x2_t out2 = vzipq_f32(a.val[1], b.val[1]); in arm_bitonic_resort_16_f32()
213 vst1q_f32(pOut, out1.val[0]); in arm_bitonic_resort_16_f32()
214 vst1q_f32(pOut+4, out1.val[1]); in arm_bitonic_resort_16_f32()
215 vst1q_f32(pOut+8, out2.val[0]); in arm_bitonic_resort_16_f32()
216 vst1q_f32(pOut+12, out2.val[1]); in arm_bitonic_resort_16_f32()
273 a = vcombine_f32(vget_low_f32(ab.val[0]), vget_low_f32(cd.val[0])); in arm_bitonic_sort_16_f32()
274 b = vcombine_f32(vget_low_f32(ab.val[1]), vget_low_f32(cd.val[1])); in arm_bitonic_sort_16_f32()
275 c = vcombine_f32(vget_high_f32(ab.val[0]), vget_high_f32(cd.val[0])); in arm_bitonic_sort_16_f32()
276 d = vcombine_f32(vget_high_f32(ab.val[1]), vget_high_f32(cd.val[1])); in arm_bitonic_sort_16_f32()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/TransformFunctions/ |
| D | arm_rfft_fast_f16.c | 113 xB.val[0] = vldrhq_gather_shifted_offset_f16(pB, vecStridesBkwd); in stage_rfft_f16()
114 xB.val[1] = vldrhq_gather_shifted_offset_f16(&pB[1], vecStridesBkwd); in stage_rfft_f16()
116 xB.val[1] = vnegq_f16(xB.val[1]); in stage_rfft_f16()
124 tmp1.val[0] = vaddq_f16(xA.val[0],xB.val[0]); in stage_rfft_f16()
125 tmp1.val[1] = vaddq_f16(xA.val[1],xB.val[1]); in stage_rfft_f16()
127 tmp2.val[0] = vsubq_f16(xB.val[0],xA.val[0]); in stage_rfft_f16()
128 tmp2.val[1] = vsubq_f16(xB.val[1],xA.val[1]); in stage_rfft_f16()
130 res.val[0] = vmulq(tw.val[0], tmp2.val[0]); in stage_rfft_f16()
131 res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); in stage_rfft_f16()
133 res.val[1] = vmulq(tw.val[0], tmp2.val[1]); in stage_rfft_f16()
[all …]
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| D | arm_rfft_fast_f32.c | 108 xB.val[0] = vldrwq_gather_shifted_offset_f32(pB, vecStridesBkwd); in stage_rfft_f32()
109 xB.val[1] = vldrwq_gather_shifted_offset_f32(&pB[1], vecStridesBkwd); in stage_rfft_f32()
111 xB.val[1] = vnegq_f32(xB.val[1]); in stage_rfft_f32()
119 tmp1.val[0] = vaddq_f32(xA.val[0],xB.val[0]); in stage_rfft_f32()
120 tmp1.val[1] = vaddq_f32(xA.val[1],xB.val[1]); in stage_rfft_f32()
122 tmp2.val[0] = vsubq_f32(xB.val[0],xA.val[0]); in stage_rfft_f32()
123 tmp2.val[1] = vsubq_f32(xB.val[1],xA.val[1]); in stage_rfft_f32()
125 res.val[0] = vmulq(tw.val[0], tmp2.val[0]); in stage_rfft_f32()
126 res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); in stage_rfft_f32()
128 res.val[1] = vmulq(tw.val[0], tmp2.val[1]); in stage_rfft_f32()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/components/lsm6dso/ |
| D | fsl_lsm.c | 15 uint8_t val = 0; in LSM_Init() local
24 if (LSM_ReadReg(handle, LSM_WHO_AM_I_REG, &val) != kStatus_Success) in LSM_Init()
29 if (val != LSM_WHO_AM_I_REG_WHO_AM_I) in LSM_Init()
34 if (LSM_ReadReg(handle, LSM_CTRL3_C_REG, &val) != kStatus_Success) in LSM_Init()
38 val |= 0x01U; in LSM_Init()
39 if (LSM_WriteReg(handle, LSM_CTRL3_C_REG, &val) != kStatus_Success) in LSM_Init()
66 if (LSM_ReadReg(handle, LSM_CTRL4_C_REG, &val) != kStatus_Success) in LSM_Init()
70 val |= 0x08U; in LSM_Init()
71 if (LSM_WriteReg(handle, LSM_CTRL4_C_REG, &val) != kStatus_Success) in LSM_Init()
83 val = LSM_PAGE_RW_REG_PAGE_WRITE(0x01U); in LSM_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/PrivateInclude/ |
| D | arm_sorting.h | 111 float32x4_t vtrn128_temp = a.val[1]; \
112 a.val[1] = b.val[0]; \
113 b.val[0] = vtrn128_temp ; \
131 a_0 = vget_low_f32(a.val[0]); \
132 a_1 = vget_high_f32(a.val[0]); \
133 a_2 = vget_low_f32(a.val[1]); \
134 a_3 = vget_high_f32(a.val[1]); \
135 b_0 = vget_low_f32(b.val[0]); \
136 b_1 = vget_high_f32(b.val[0]); \
137 b_2 = vget_low_f32(b.val[1]); \
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/components/mma8451q/ |
| D | fsl_mma.c | 19 uint8_t val = 0; in MMA_Init() local
28 if (MMA_ReadReg(handle, kMMA8451_WHO_AM_I, &val) != kStatus_Success) in MMA_Init()
33 if (val != kMMA8451_WHO_AM_I_Device_ID) in MMA_Init()
39 if (MMA_ReadReg(handle, kMMA8451_CTRL_REG2, &val) != kStatus_Success) in MMA_Init()
43 val |= (uint8_t)0x40; in MMA_Init()
44 if (MMA_WriteReg(handle, kMMA8451_CTRL_REG2, val) != kStatus_Success) in MMA_Init()
54 if (MMA_ReadReg(handle, kMMA8451_CTRL_REG1, &val) != kStatus_Success) in MMA_Init()
58 val &= (uint8_t)(~(0x01)); in MMA_Init()
59 if (MMA_WriteReg(handle, kMMA8451_CTRL_REG1, val) != kStatus_Success) in MMA_Init()
64 if (MMA_ReadReg(handle, kMMA8451_XYZ_DATA_CFG, &val) != kStatus_Success) in MMA_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Include/ |
| D | arm_math_memory.h | 79 q31_t val; in read_q15x2() local
82 memcpy (&val, pQ15, 4); in read_q15x2()
84 val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; in read_q15x2()
87 return (val); in read_q15x2()
98 q31_t val; in read_q15x2_ia() local
101 memcpy (&val, *pQ15, 4); in read_q15x2_ia()
103 val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); in read_q15x2_ia()
107 return (val); in read_q15x2_ia()
118 q31_t val; in read_q15x2_da() local
121 memcpy (&val, *pQ15, 4); in read_q15x2_da()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/components/mma8652fc/ |
| D | fsl_mma.c | 19 uint8_t val = 0; in MMA_Init() local
27 if (MMA_ReadReg(handle, (uint8_t)kMMA8652_WHO_AM_I, &val) != kStatus_Success) in MMA_Init()
32 if (val != (uint8_t)kMMA8652_WHO_AM_I_Device_ID) in MMA_Init()
38 if (MMA_ReadReg(handle, (uint8_t)kMMA8652_CTRL_REG1, &val) != kStatus_Success) in MMA_Init()
42 val &= (uint8_t)~0x01U; in MMA_Init()
43 if (MMA_WriteReg(handle, (uint8_t)kMMA8652_CTRL_REG1, val) != kStatus_Success) in MMA_Init()
48 if (MMA_ReadReg(handle, (uint8_t)kMMA8652_XYZ_DATA_CFG, &val) != kStatus_Success) in MMA_Init()
52 val &= (uint8_t)~0x03U; in MMA_Init()
53 val |= 0x01U; in MMA_Init()
54 if (MMA_WriteReg(handle, (uint8_t)kMMA8652_XYZ_DATA_CFG, val) != kStatus_Success) in MMA_Init()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/ |
| D | evkmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 41 unsigned int val;
44 val = MEM_ReadU32(0x40C84820);
45 val &= ~(0x10000 | 0xFF);
46 MEM_WriteU32(0x40C84820, val);
52 val = MEM_ReadU32(0x40C84500);
53 val ^= 0x10000;
54 MEM_WriteU32(0x40C84500, val);
59 unsigned int val;
63 val = MEM_ReadU32(0x40C84270);
64 if (((val & 0x8000) != 0) || (((val & 0x3F00) >> 8) != 16))
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/ |
| D | evkbmimxrt1170_connect_cm4_cm4side_sdram.jlinkscript | 41 unsigned int val;
44 val = MEM_ReadU32(0x40C84820);
45 val &= ~(0x10000 | 0xFF);
46 MEM_WriteU32(0x40C84820, val);
52 val = MEM_ReadU32(0x40C84500);
53 val ^= 0x10000;
54 MEM_WriteU32(0x40C84500, val);
59 unsigned int val;
63 val = MEM_ReadU32(0x40C84270);
64 if (((val & 0x8000) != 0) || (((val & 0x3F00) >> 8) != 16))
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/powerquad/ |
| D | fsl_powerquad.h | 1789 pq_float_t val; in PQ_LnF32() local
1791 val.floatX = *pSrc; in PQ_LnF32()
1792 _pq_ln0(val.integerX); in PQ_LnF32()
1793 val.integerX = _pq_readAdd0(); in PQ_LnF32()
1794 *pDst = val.floatX; in PQ_LnF32()
1805 pq_float_t val; in PQ_InvF32() local
1807 val.floatX = *pSrc; in PQ_InvF32()
1808 _pq_inv0(val.integerX); in PQ_InvF32()
1809 val.integerX = _pq_readMult0(); in PQ_InvF32()
1810 *pDst = val.floatX; in PQ_InvF32()
[all …]
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| D | fsl_powerquad_math.c | 25 pq_float_t val; in PQ_VectorLnF32() local
32 val.floatX = *pSrc++; in PQ_VectorLnF32()
33 _pq_ln0(val.integerX); in PQ_VectorLnF32()
34 val.integerX = _pq_readAdd0(); in PQ_VectorLnF32()
35 *pDst++ = val.floatX; in PQ_VectorLnF32()
50 pq_float_t val; in PQ_VectorInvF32() local
57 val.floatX = *pSrc++; in PQ_VectorInvF32()
58 _pq_inv0(val.integerX); in PQ_VectorInvF32()
59 val.integerX = _pq_readMult0(); in PQ_VectorInvF32()
60 *pDst++ = val.floatX; in PQ_VectorInvF32()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/components/codec/wm8960/ |
| D | fsl_wm8960.c | 442 uint16_t val = 0; in WM8960_SetLeftInput() local
447 WM8960_CHECK_RET(WM8960_ReadReg(WM8960_POWER1, &val), ret); in WM8960_SetLeftInput()
448 val &= (uint16_t) ~(WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); in WM8960_SetLeftInput()
449 WM8960_CHECK_RET(WM8960_WriteReg(handle, WM8960_POWER1, val), ret); in WM8960_SetLeftInput()
453 WM8960_CHECK_RET(WM8960_ReadReg(WM8960_POWER1, &val), ret); in WM8960_SetLeftInput()
454 val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); in WM8960_SetLeftInput()
455 WM8960_CHECK_RET(WM8960_WriteReg(handle, WM8960_POWER1, val), ret); in WM8960_SetLeftInput()
460 WM8960_CHECK_RET(WM8960_ReadReg(WM8960_POWER1, &val), ret); in WM8960_SetLeftInput()
461 val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); in WM8960_SetLeftInput()
462 WM8960_CHECK_RET(WM8960_WriteReg(handle, WM8960_POWER1, val), ret); in WM8960_SetLeftInput()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/sdma/ |
| D | fsl_sdma.c | 26 #define SDMA_P2P_LOW_WATERMARK(val) ((uint32_t)(val)&SDMA_P2P_LOW_WATERMARK_MASK) argument
30 #define SDMA_P2P_HIGH_WATERMARK(val) (((uint32_t)(val) << SDMA_P2P_HIGH_WATERMARK_SHIFT) & SDMA_P2… argument
34 #define SDMA_P2P_SOURCE_SPBA_VAL(val) (((uint32_t)(val) << SDMA_P2P_SOURCE_SPBA_SHIFT) & SDMA_P2P_S… argument
38 #define SDMA_P2P_DEST_SPBA(val) (((uint32_t)(val) << SDMA_P2P_DEST_SPBA_SHIFT) & SDMA_P2P_DEST_SPB… argument
42 #define SDMA_P2P_LOWER_EVENT_REG(val) \ argument
43 (((uint32_t)(val) << SDMA_P2P_LOWER_EVENT_REG_SHIFT) & SDMA_P2P_LOWER_EVENT_REG_MASK)
47 #define SDMA_P2P_HIGHER_EVENT_REG(val) \ argument
48 (((uint32_t)(val) << SDMA_P2P_HIGHER_EVENT_REG_SHIFT) & SDMA_P2P_HIGHER_EVENT_REG_MASK)
52 #define SDMA_P2P_CONT(val) (((uint32_t)(val) << SDMA_P2P_CONT_SHIFT) & SDMA_P2P_CONT_MASK) argument
156 uint32_t val = 0; in SDMA_GetScriptAddr() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/components/codec/cs42448/ |
| D | fsl_cs42448.c | 279 uint8_t val = 0; in CS42448_ConfigDataFormat() local
282 if (CS42448_ReadReg(handle, CS42448_FUNCTIONAL_MODE, &val) != kStatus_Success) in CS42448_ConfigDataFormat()
288 val &= (uint8_t)~0xEU; in CS42448_ConfigDataFormat()
300 val |= 4U; in CS42448_ConfigDataFormat()
307 val |= 4U; in CS42448_ConfigDataFormat()
312 val |= 8U; in CS42448_ConfigDataFormat()
319 val |= 4U; in CS42448_ConfigDataFormat()
324 val |= 8U; in CS42448_ConfigDataFormat()
331 val |= 8U; in CS42448_ConfigDataFormat()
339 retval = CS42448_WriteReg(handle, CS42448_FUNCTIONAL_MODE, val); in CS42448_ConfigDataFormat()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/components/codec/cs42888/ |
| D | fsl_cs42888.c | 282 uint8_t val = 0; in CS42888_ConfigDataFormat() local
285 if (CS42888_ReadReg(handle, CS42888_FUNCTIONAL_MODE, &val) != kStatus_Success) in CS42888_ConfigDataFormat()
291 val &= (uint8_t)~0xEU; in CS42888_ConfigDataFormat()
303 val |= 4U; in CS42888_ConfigDataFormat()
310 val |= 4U; in CS42888_ConfigDataFormat()
315 val |= 8U; in CS42888_ConfigDataFormat()
322 val |= 4U; in CS42888_ConfigDataFormat()
327 val |= 8U; in CS42888_ConfigDataFormat()
334 val |= 8U; in CS42888_ConfigDataFormat()
342 retval = CS42888_WriteReg(handle, CS42888_FUNCTIONAL_MODE, val); in CS42888_ConfigDataFormat()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi_flr/ |
| D | fsl_flexspi_flr.h | 192 static inline void FLEXSPI_SLV_SoftwareReset_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) in FLEXSPI_SLV_SoftwareReset_SetVal() argument
195 base->MODULE_CONTROL |= FLEXSPI_SLV_MODULE_CONTROL_SWRESET(val); in FLEXSPI_SLV_SoftwareReset_SetVal()
206 static inline void FLEXSPI_SLV_IOMode_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) in FLEXSPI_SLV_IOMode_SetVal() argument
209 base->MODULE_CONTROL |= FLEXSPI_SLV_MODULE_CONTROL_IOMODE(val); in FLEXSPI_SLV_IOMode_SetVal()
232 static inline void FLEXSPI_SLV_RW_CMD_BaseAddr1_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) in FLEXSPI_SLV_RW_CMD_BaseAddr1_SetVal() argument
235 base->RW_COMMAND_BASE |= FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE1(val); in FLEXSPI_SLV_RW_CMD_BaseAddr1_SetVal()
246 static inline void FLEXSPI_SLV_RW_CMD_BaseAddr2_SetVal(FLEXSPI_SLV_Type *base, uint32_t val) in FLEXSPI_SLV_RW_CMD_BaseAddr2_SetVal() argument
249 base->RW_COMMAND_BASE |= FLEXSPI_SLV_RW_COMMAND_BASE_ADDRBASE2(val); in FLEXSPI_SLV_RW_CMD_BaseAddr2_SetVal()
261 static inline void FLEXSPI_SLV_AddrRange_SetVal(FLEXSPI_SLV_Type *base, uint32_t i, uint32_t val) in FLEXSPI_SLV_AddrRange_SetVal() argument
263 base->CMD_RANGE[i] = FLEXSPI_SLV_CMD_RANGE_RANGE(val); in FLEXSPI_SLV_AddrRange_SetVal()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/NN/Include/ |
| D | arm_nnsupportfunctions.h | 493 q31_t val; in arm_nn_read_q15x2_ia() local
495 memcpy(&val, *in_q15, 4); in arm_nn_read_q15x2_ia()
498 return (val); in arm_nn_read_q15x2_ia()
508 q31_t val; in arm_nn_read_q7x4_ia() local
509 memcpy(&val, *in_q7, 4); in arm_nn_read_q7x4_ia()
512 return (val); in arm_nn_read_q7x4_ia()
522 q31_t val; in arm_nn_read_q15x2() local
523 memcpy(&val, in_q15, 4); in arm_nn_read_q15x2()
525 return (val); in arm_nn_read_q15x2()
535 q31_t val; in arm_nn_read_q7x4() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/common/ |
| D | fsl_common_arm.h | 70 #define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ argument
73 (val) = __LDREXB(addr); \
75 } while (0UL != __STREXB((val), (addr)))
77 #define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ argument
80 (val) = __LDREXH(addr); \
82 } while (0UL != __STREXH((val), (addr)))
84 #define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ argument
87 (val) = __LDREXW(addr); \
89 } while (0UL != __STREXW((val), (addr)))
91 static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) in _SDK_AtomicLocalAdd1Byte() argument
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/ |
| D | fsl_power.c | 49 #define POWER_WRITE_MEM32(addr, val) \ argument
52 *((volatile uint32_t *)(addr)) = (val); \
939 uint32_t val; in POWER_InitVSensorThreshold() local
948 val = SENSOR_CTRL->VSEN_CTRL_1_REG_1; in POWER_InitVSensorThreshold()
949 SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK; in POWER_InitVSensorThreshold()
952 val = val & ~(SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR_MASK | in POWER_InitVSensorThreshold()
954 val |= SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR( in POWER_InitVSensorThreshold()
956 …val |= SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR((v11.param1 * (svcMv * 10U - v11.margin)… in POWER_InitVSensorThreshold()
958 SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK; in POWER_InitVSensorThreshold()
960 SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val; in POWER_InitVSensorThreshold()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/ |
| D | fsl_power.c | 49 #define POWER_WRITE_MEM32(addr, val) \ argument
52 *((volatile uint32_t *)(addr)) = (val); \
939 uint32_t val; in POWER_InitVSensorThreshold() local
948 val = SENSOR_CTRL->VSEN_CTRL_1_REG_1; in POWER_InitVSensorThreshold()
949 SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK; in POWER_InitVSensorThreshold()
952 val = val & ~(SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR_MASK | in POWER_InitVSensorThreshold()
954 val |= SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MAX_VOLTAGE_THR( in POWER_InitVSensorThreshold()
956 …val |= SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_MIN_VOLTAGE_THR((v11.param1 * (svcMv * 10U - v11.margin)… in POWER_InitVSensorThreshold()
958 SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val & ~SENSOR_CTRL_VSEN_CTRL_1_REG_1_VSEN_SW_ENABLE_MASK; in POWER_InitVSensorThreshold()
960 SENSOR_CTRL->VSEN_CTRL_1_REG_1 = val; in POWER_InitVSensorThreshold()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/ |
| D | timer_armv8a.h | 59 __STATIC_INLINE void ARM_TIMER_SetInterval(ARM_TIMER_type_t timer, uint32_t val) in ARM_TIMER_SetInterval() argument
63 __MSR(CNTP_TVAL_EL0, val); in ARM_TIMER_SetInterval()
66 __MSR(CNTV_TVAL_EL0, val); in ARM_TIMER_SetInterval()
69 __MSR(CNTHP_TVAL_EL2, val); in ARM_TIMER_SetInterval()
72 __MSR(CNTPS_TVAL_EL1, val); in ARM_TIMER_SetInterval()
82 __STATIC_INLINE void ARM_TIMER_GetCount(ARM_TIMER_type_t timer, uint32_t *val) in ARM_TIMER_GetCount() argument
86 __MRS(CNTP_TVAL_EL0, val); in ARM_TIMER_GetCount()
89 __MRS(CNTV_TVAL_EL0, val); in ARM_TIMER_GetCount()
92 __MRS(CNTHP_TVAL_EL2, val); in ARM_TIMER_GetCount()
95 __MRS(CNTPS_TVAL_EL1, val); in ARM_TIMER_GetCount()
[all …]
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/src/ |
| D | OsIf_Timer_System_Internal_GenericTimer.c | 169 static void write_CNTFRQ(uint32 val);
170 static void write_CNTFRQ(uint32 val) in write_CNTFRQ() argument
173 uint64 val64 = val; in write_CNTFRQ()
190 static void write_CNTP_CTL(uint32 val);
191 static void write_CNTP_CTL(uint32 val) in write_CNTP_CTL() argument
194 uint64 val64 = val; in write_CNTP_CTL()
211 static void write_CNTP_TVAL(uint32 val);
212 static void write_CNTP_TVAL(uint32 val) in write_CNTP_TVAL() argument
215 uint64 val64 = val; in write_CNTP_TVAL()
252 static void write_CNTP_CTL(uint32 val);
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/RTOS2/RTX/Source/ |
| D | rtx_core_ca.h | 430 static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { in atomic_wr8() argument
440 __STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { in atomic_wr8() argument
462 [val] "l" (val) in atomic_wr8()
490 register uint32_t val, res; in atomic_set32() local
507 [val] "=&l" (val), in atomic_set32()
539 register uint32_t val, res; in atomic_clr32() local
556 [val] "=&l" (val), in atomic_clr32()
595 register uint32_t val, res; in atomic_chk32_all() local
620 [val] "=&l" (val), in atomic_chk32_all()
658 register uint32_t val, res; in atomic_chk32_any() local
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| /hal_nxp-latest/mcux/middleware/wifi_nxp/cli/ |
| D | cli_utils.c | 66 uint32_t val = 0; in a2hex() local
75 val = (val << 4) + hexc2bin(*s++); in a2hex()
77 return val; in a2hex()
113 unsigned int val = 0; in get_uint() local
121 val *= 10U; in get_uint()
122 val += (unsigned int)arg[i] - (unsigned int)'0'; in get_uint()
125 *dest = val; in get_uint()
187 uint8_t val = 0; in get_channel_list() local
201 chan_number[count] = val; in get_channel_list()
203 val = 0; in get_channel_list()
[all …]
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