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Searched refs:XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1010/
Dclock_config.c150 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
444 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1015/
Dclock_config.c155 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
466 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1020/
Dclock_config.c166 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
541 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1024/
Dclock_config.c166 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
541 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1040/
Dclock_config.c177 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
603 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_600M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbimxrt1050/
Dclock_config.c174 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
619 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1060/
Dclock_config.c181 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
640 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1064/
Dclock_config.c183 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
644 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkcmimxrt1060/
Dclock_config.c180 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
639 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1060/
Dclock_config.c181 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN()
640 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h35979 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
35981 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h39069 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
39071 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h46143 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
46145 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h46164 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
46166 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h48262 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
48264 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h49231 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
49233 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h52528 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
52530 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h52641 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
52643 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h50622 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
50624 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h54752 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
54754 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h54816 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) macro
54818 …(uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h40178 #define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK 0x10000u macro