| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/ |
| D | MIMX8QX2_cm4.h | 51310 #define CM4__INTMUX_BASE (0x41400000u) macro 51312 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51318 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/ |
| D | MIMX8QX1_cm4.h | 51310 #define CM4__INTMUX_BASE (0x41400000u) macro 51312 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51318 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/ |
| D | MIMX8DX1_cm4.h | 51310 #define CM4__INTMUX_BASE (0x41400000u) macro 51312 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51318 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/ |
| D | MIMX8DX2_cm4.h | 51310 #define CM4__INTMUX_BASE (0x41400000u) macro 51312 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51318 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/ |
| D | MIMX8QX3_cm4.h | 51873 #define CM4__INTMUX_BASE (0x41400000u) macro 51875 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51881 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/ |
| D | MIMX8DX4_cm4.h | 51873 #define CM4__INTMUX_BASE (0x41400000u) macro 51875 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51881 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/ |
| D | MIMX8DX3_cm4.h | 51873 #define CM4__INTMUX_BASE (0x41400000u) macro 51875 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51881 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/ |
| D | MIMX8QX6_dsp.h | 53106 #define CM4__INTMUX_BASE (0x37400000u) macro 53108 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 53114 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| D | MIMX8QX6_cm4.h | 51875 #define CM4__INTMUX_BASE (0x41400000u) macro 51877 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51883 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/ |
| D | MIMX8DX6_cm4.h | 51875 #define CM4__INTMUX_BASE (0x41400000u) macro 51877 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51883 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/ |
| D | MIMX8QX5_cm4.h | 51874 #define CM4__INTMUX_BASE (0x41400000u) macro 51876 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51882 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/ |
| D | MIMX8DX5_cm4.h | 51875 #define CM4__INTMUX_BASE (0x41400000u) macro 51877 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51883 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/ |
| D | MIMX8UX6_cm4.h | 51876 #define CM4__INTMUX_BASE (0x41400000u) macro 51878 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51884 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/ |
| D | MIMX8UX5_cm4.h | 51876 #define CM4__INTMUX_BASE (0x41400000u) macro 51878 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51884 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/ |
| D | MIMX8QX4_cm4.h | 51872 #define CM4__INTMUX_BASE (0x41400000u) macro 51874 #define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE) 51880 #define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
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