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Searched refs:CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h5304 #define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK (0x40000000U) macro
5310 …t32_t)(x)) << CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK)
DMIMXRT595S_cm33.h11561 #define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK (0x40000000U) macro
11567 …t32_t)(x)) << CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h11557 #define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK (0x40000000U) macro
11563 …t32_t)(x)) << CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h11560 #define CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK (0x40000000U) macro
11566 …t32_t)(x)) << CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_SHIFT)) & CLKCTL1_PSCCTL2_CLR_GPIOINTCTL_CLK_MASK)