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Searched refs:PLL_DDR (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.7.0/imx/drivers/
Dccm_analog_imx7d.h65 …ccmAnalogPllDdrControl = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT), /*!<…
82 …ccmAnalogPllDdrClock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT), …
83 …ccmAnalogPllDdrDiv2Clock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT),…
/hal_nxp-3.7.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h8569 …__IO uint32_t PLL_DDR; /**< Anadig DDR PLL Control Register, offse… member
8635 #define CCM_ANALOG_PLL_DDR_REG(base) ((base)->PLL_DDR)