Searched refs:MUX_2_DC_3 (Results 1 – 2 of 2) sorted by relevance
2250 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency()2251 …Frequency /= (((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHI… in Clock_Ip_Get_P0_PSI5_S_UTIL_CLK_Frequency()2267 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DE_MASK) >> … in Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency()2268 …Frequency /= (((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHI… in Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency()3840 …Frequency /= (((IP_MC_CGM_0->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHI… in Clock_Ip_Get_PSI5S_0_CLK_Frequency()3850 …Frequency /= (((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DIV_MASK) >> MC_CGM_MUX_2_DC_3_DIV_SHI… in Clock_Ip_Get_PSI5S_1_CLK_Frequency()
104 …__IO uint32_t MUX_2_DC_3; /**< Clock Mux 2 Divider 3 Control Register, offs… member