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/Zephyr-latest/arch/riscv/core/
Duserspace.S28 li a5, 0 # Counter
29 sw a5, 0(a2) # Init error value to 0
32 add a4, a0, a5 # Determine character address
38 bne a5, a1, continue # Check if max length is reached
41 mv a0, a5 # Return counter value (length)
45 addi a5, a5, 1 # Increment counter
Dcoredump.c30 uint64_t a5; member
51 uint32_t a5;
100 arch_blk.r.a5 = esf->a5; in arch_coredump_info_dump()
Dfatal.c112 LOG_ERR(" a5: " PR_REG, esf->a5); in z_riscv_fatal_error_csf()
116 LOG_ERR(" a5: " PR_REG " t5: " PR_REG, esf->a5, esf->t5); in z_riscv_fatal_error_csf()
/Zephyr-latest/arch/xtensa/core/
Dwindow_vectors.S56 s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
57 s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */
58 s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
59 s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */
78 l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
79 l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */
80 l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
81 l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */
140 s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */
169 l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */
[all …]
Dsyscall_helper.c24 register uintptr_t a5 __asm__("%a5") = arg4; in xtensa_syscall_helper_args_6()
31 "r" (a5), "r" (a8), "r" (a9) in xtensa_syscall_helper_args_6()
45 register uintptr_t a5 __asm__("%a5") = arg4; in xtensa_syscall_helper_args_5()
51 "r" (a5), "r" (a8) in xtensa_syscall_helper_args_5()
65 register uintptr_t a5 __asm__("%a5") = arg4; in xtensa_syscall_helper_args_4()
70 "r" (a5) in xtensa_syscall_helper_args_4()
Ddebug_helpers_asm.S27 l32i a6, a5, 0
Dcoredump.c70 uint32_t a5; member
160 arch_blk.r.a5 = frame->blks[regs_blk_remaining].r1; in arch_coredump_info_dump()
Dcrt1.S36 # define ARG4 a5 /* 4th outgoing call argument */
/Zephyr-latest/arch/xtensa/core/startup/
Dreset_vector.S109 movi a5, CORE_STATE_SIGNATURE
118 sub a4, a4, a5
240 sub a4, a4, a5
249 addi a5, a7, - PWRSTAT_WAKEUP_RESET
251 movnez a7, a5, a4
412 extui a5, a8, 0, 2 /* lower two bit indicate whether cached */
415 moveqz a9, a10, a5 /* ... that region is non-cacheable */
416 addx4 a5, a8, a3 /* index into _xtos_mpu_attribs table */
418 movgez a5, a3, a8 /* if not valid attrib, use Illegal */
419 l32i a5, a5, 0 /* load access rights, memtype from table
[all …]
/Zephyr-latest/include/zephyr/arch/arm64/
Darm-smccc.h20 unsigned long a5; member
42 unsigned long a4, unsigned long a5,
55 unsigned long a4, unsigned long a5,
/Zephyr-latest/tests/drivers/tee/optee/src/
Dmain.c33 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7,
45 uint32_t a5; member
55 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, in arm_smccc_smc() argument
75 t_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
78 wait_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
81 send_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
87 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, in arm_smccc_hvc() argument
115 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, in fast_call() argument
123 t_call.a5 = a5; in fast_call()
131 unsigned long a4, unsigned long a5, unsigned long a6, unsigned long a7, in fail_call() argument
[all …]
/Zephyr-latest/tests/bluetooth/controller/ctrl_sw_privacy_unit/src/
Dmain.c48 bt_addr_t a1, a2, a3, a4, a5; in helper_prpa_add() local
55 bt_addr_copy(&a5, BT_ADDR_INIT(0x52, 0x53, 0x54, 0x55, 0x56, 0x57)); in helper_prpa_add()
79 prpa_cache_add(&a5); in helper_prpa_add()
80 pos = prpa_cache_find(&a5); in helper_prpa_add()
91 bt_addr_t a1, a2, a3, a4, a5; in helper_trpa_add() local
98 bt_addr_copy(&a5, BT_ADDR_INIT(0x52, 0x53, 0x54, 0x55, 0x56, 0x57)); in helper_trpa_add()
122 trpa_cache_add(&a5, 4); in helper_trpa_add()
123 pos = trpa_cache_find(&a5, 4); in helper_trpa_add()
/Zephyr-latest/drivers/console/
Dxtensa_sim_console.c25 register int a5 __asm__ ("a5") = 1; in arch_printk_char_out()
32 : "a" (a2), "a" (a3), "a" (a4), "a" (a5) in arch_printk_char_out()
Dwinstream_console.c32 register int a5 __asm__("a5") = len; in winstream_console_trace_out()
34 __asm__ volatile("simcall" : "+r"(a2), "+r"(a3) : "r"(a4), "r"(a5) : "memory"); in winstream_console_trace_out()
/Zephyr-latest/include/zephyr/arch/xtensa/
Dsyscall.h74 register uintptr_t a5 __asm__("%a5") = arg4; in arch_syscall_invoke6()
81 "r" (a5), "r" (a8), "r" (a9) in arch_syscall_invoke6()
99 register uintptr_t a5 __asm__("%a5") = arg4; in arch_syscall_invoke5()
105 "r" (a5), "r" (a8) in arch_syscall_invoke5()
123 register uintptr_t a5 __asm__("%a5") = arg4; in arch_syscall_invoke4()
128 "r" (a5) in arch_syscall_invoke4()
/Zephyr-latest/samples/drivers/spi_bitbang/
DREADME.rst39 wrote 0101 00ff 00a5 0000 0102
45 wrote 0101 00ff 00a5 0000 0102
51 wrote 0101 00ff 00a5 0000 0102
/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_context.h195 uintptr_t a5; member
216 uintptr_t a5; member
232 uintptr_t a5; member
/Zephyr-latest/subsys/logging/backends/
Dlog_backend_xtensa_sim.c28 register int a5 __asm__ ("a5") = length; in char_out()
32 : "a"(a2), "a"(a3), "a"(a4), "a"(a5)); in char_out()
/Zephyr-latest/include/zephyr/drivers/sip_svc/
Dsip_svc_driver.h73 unsigned long *a4, unsigned long *a5, unsigned long *a6,
272 unsigned long *a4, unsigned long *a5, unsigned long *a6,
277 unsigned long *a5, unsigned long *a6, in z_impl_sip_svc_plat_async_res_req() argument
290 __ASSERT(a5, "a5 shouldn't be NULL"); in z_impl_sip_svc_plat_async_res_req()
295 return api->sip_svc_plat_async_res_req(dev, a0, a1, a2, a3, a4, a5, a6, a7, buf, size); in z_impl_sip_svc_plat_async_res_req()
Dsip_svc_proto.h140 unsigned long a5; member
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h31 unsigned long a5; \
53 unsigned long a5; \
/Zephyr-latest/tests/lib/cmsis_dsp/common/
Dtest_common.h53 #define DEFINE_TEST_VARIANT5(suite, name, variant, a1, a2, a3, a4, a5) \ argument
56 test_##name(a1, a2, a3, a4, a5); \
59 #define DEFINE_TEST_VARIANT6(suite, name, variant, a1, a2, a3, a4, a5, a6) \ argument
62 test_##name(a1, a2, a3, a4, a5, a6); \
65 #define DEFINE_TEST_VARIANT7(suite, name, variant, a1, a2, a3, a4, a5, a6, a7) \ argument
68 test_##name(a1, a2, a3, a4, a5, a6, a7); \
/Zephyr-latest/include/zephyr/arch/riscv/
Dexception.h75 unsigned long a5; /* function argument */ member
Dsyscall.h49 register unsigned long a5 __asm__ ("a5") = arg6; in arch_syscall_invoke6()
54 : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), in arch_syscall_invoke6()
/Zephyr-latest/drivers/sip_svc/
Dsip_smc_intel_socfpga.c119 unsigned long *a4, unsigned long *a5, unsigned long *a6, in intel_sip_smc_plat_async_res_req() argument
200 LOG_DBG("\tres->a5 %08lx", res->a5); in intel_sip_secure_monitor_call()

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