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Searched refs:uint8 (Results 1 – 25 of 162) sorted by relevance

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/hal_nxp-3.5.0/s32/drivers/s32k3/Eth_GMAC/include/
DGmac_Ip.h113 Gmac_Ip_StatusType Gmac_Ip_Init(uint8 Instance,
123 void Gmac_Ip_Deinit(uint8 Instance);
131 Gmac_Ip_PowerStateType Gmac_Ip_GetPowerState(uint8 Instance);
139 void Gmac_Ip_SetPowerState(uint8 Instance, Gmac_Ip_PowerStateType PowerState);
146 void Gmac_Ip_EnableController(uint8 Instance);
158 Gmac_Ip_StatusType Gmac_Ip_DisableController(uint8 Instance);
166 void Gmac_Ip_SetSpeed(uint8 Instance, Gmac_Ip_SpeedType Speed);
191 Gmac_Ip_StatusType Gmac_Ip_GetTxBuff(uint8 Instance,
192 uint8 Ring,
217 Gmac_Ip_StatusType Gmac_Ip_SendFrame(uint8 Instance,
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/hal_nxp-3.5.0/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip.h126 void Emios_Pwm_Ip_InitChannel(uint8 Instance,
136 void Emios_Pwm_Ip_DeInitChannel(uint8 Instance,
137 uint8 Channel);
148 void Emios_Pwm_Ip_ForceMatchLeadingEdge(uint8 Instance,
149 uint8 Channel,
161 void Emios_Pwm_Ip_ForceMatchTrailingEdge(uint8 Instance,
162 uint8 Channel,
173 Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetPeriod(uint8 Instance,
174 uint8 Channel);
184 void Emios_Pwm_Ip_SetPeriod(uint8 Instance,
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DEmios_Pwm_Ip_HwAccess.h152 uint8 Channel, in Emios_Pwm_Ip_SetOutputUpdate()
164 uint8 Channel) in Emios_Pwm_Ip_GetOutputUpdate()
186 uint8 Channel, in Emios_Pwm_Ip_SetChannelEnable()
199 uint8 Channel) in Emios_Pwm_Ip_GetChannelEnable()
212 uint8 Channel, in Emios_Pwm_Ip_SetUCRegA()
225 uint8 Channel) in Emios_Pwm_Ip_GetUCRegA()
238 uint8 Channel, in Emios_Pwm_Ip_SetUCRegB()
251 uint8 Channel) in Emios_Pwm_Ip_GetUCRegB()
264 uint8 Channel) in Emios_Pwm_Ip_GetInternalCounterValue()
279 uint8 Channel, in Emios_Pwm_Ip_SetFreezeEnable()
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/hal_nxp-3.5.0/s32/drivers/s32k3/Icu/include/
DEmios_Icu_Ip.h164 eMios_Icu_Ip_StatusType Emios_Icu_Ip_Init(uint8 instance, const eMios_Icu_Ip_ConfigType *userConfig…
176 eMios_Icu_Ip_StatusType Emios_Icu_Ip_Deinit(uint8 instance);
192 void Emios_Icu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel);
202 void Emios_Icu_Ip_SetNormalMode(uint8 instance, uint8 hwChannel);
214 void Emios_Icu_Ip_SetActivation(uint8 instance, uint8 hwChannel, eMios_Icu_Ip_EdgeType edge);
226 void Emios_Icu_Ip_EnableEdgeDetection(uint8 instance, uint8 hwChannel);
237 void Emios_Icu_Ip_DisableEdgeDetection(uint8 instance, uint8 hwChannel);
247 void Emios_Icu_Ip_EnableNotification(uint8 instance, uint8 hwChannel);
256 void Emios_Icu_Ip_DisableNotification(uint8 instance, uint8 hwChannel);
276 uint8 instance,
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DSiul2_Icu_Ip.h150 Siul2_Icu_Ip_StatusType Siul2_Icu_Ip_DeInit(uint8 instance);
166 Siul2_Icu_Ip_StatusType Siul2_Icu_Ip_Init(uint8 instance, const Siul2_Icu_Ip_ConfigType* userConfig…
177 void Siul2_Icu_Ip_SetActivationCondition(uint8 instance, uint8 hwChannel, Siul2_Icu_Ip_EdgeType edg…
187 boolean Siul2_Icu_Ip_GetInputState(uint8 instance, uint8 hwChannel);
198 void Siul2_Icu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel);
208 void Siul2_Icu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel);
219 void Siul2_Icu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel);
230 void Siul2_Icu_Ip_SetNormalMode(uint8 instance, uint8 HwChannel);
243 void Siul2_Icu_Ip_SetClockMode(uint8 instance, Siul2_Icu_Ip_ClockModeType mode);
253 void Siul2_Icu_Ip_EnableNotification(uint8 instance, uint8 hwChannel);
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DWkpu_Ip.h154 void Wkpu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel);
165 void Wkpu_Ip_SetNormalMode(uint8 instance, uint8 hwChannel);
176 void Wkpu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel);
186 void Wkpu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel);
199 Wkpu_Ip_StatusType Wkpu_Ip_Init(uint8 instance, const Wkpu_Ip_IrqConfigType* userConfig);
213 Wkpu_Ip_StatusType Wkpu_Ip_DeInit(uint8 instance);
225 void Wkpu_Ip_SetActivationCondition(uint8 instance, uint8 hwChannel, Wkpu_Ip_EdgeType edge);
239 boolean Wkpu_Ip_GetInputState(uint8 instance, uint8 hwChannel);
244 void Wkpu_Ip_EnableNotification(uint8 hwChannel);
249 void Wkpu_Ip_DisableNotification(uint8 hwChannel);
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/hal_nxp-3.5.0/s32/drivers/s32ze/EthSwt_NETC/include/
DNetc_EthSwt_Ip.h181 Std_ReturnType Netc_EthSwt_Ip_Init(uint8 SwitchIdx, const Netc_EthSwt_Ip_ConfigType * Config);
200 Std_ReturnType Netc_EthSwt_Ip_ReadTrcvRegister( uint8 SwitchIdx, uint8 TrcvIdx, uint8 RegIdx, uint1…
219 Std_ReturnType Netc_EthSwt_Ip_WriteTrcvRegister( uint8 SwitchIdx, uint8 TrcvIdx, uint8 RegIdx, uint…
235 Std_ReturnType Netc_EthSwt_Ip_SetPortMode(uint8 SwitchIdx,
236 uint8 SwitchPortIdx,
258 Std_ReturnType Netc_EthSwt_Ip_GetPortMode( uint8 SwitchIdx,
259 uint8 SwitchPortIdx,
282 Std_ReturnType Netc_EthSwt_Ip_GetPortSpeed( uint8 SwitchIdx,
283 uint8 SwitchPortIdx,
305 Std_ReturnType Netc_EthSwt_Ip_SetPortSpeed( uint8 SwitchIdx, uint8 SwitchPortIdx, EthTrcv_BaudRateT…
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DNetc_EthSwt_Ip_Types.h135 typedef void (*Netc_EthSwt_Ip_CallbackType)(uint8 Instance);
140 typedef void (*Netc_EthSwt_Ip_ChCallbackType)(uint8 Instance, uint8 Channel);
158 uint8 MacAddr[6]; /*!< MAC Address */
162 uint8 CutThroughDisable; /*!< CTD */
163 uint8 OverridETEID; /*!< OETEID */
164 uint8 EgressPort; /*!< EPORT */
180 uint8 SpanningTreeGroupMemberId; /*!< STG_ID */
181 uint8 MacForwardingOptions; /*!< MFO */
182 uint8 MacLearningOptions; /*!< MLO */
404 …uint8 CmdCompletionInt; /*!< CCI (Command Completion Interrupt) in con…
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/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/include/
DEth_GeneralTypes.h145 ETHTRCV_LINK_STATE_DOWN = (uint8)0x0U,
147 ETHTRCV_LINK_STATE_ACTIVE = (uint8)0x1U
158 ETHTRCV_STATE_UNINIT = (uint8)0x0U,
160 ETHTRCV_STATE_INIT = (uint8)0x1U
171 ETHTRCV_BAUD_RATE_10MBIT = (uint8)0x0U,
173 ETHTRCV_BAUD_RATE_100MBIT = (uint8)0x1U,
175 ETHTRCV_BAUD_RATE_1000MBIT = (uint8)0x2U,
188 ETHTRCV_DUPLEX_MODE_HALF = (uint8)0x0U,
190 ETHTRCV_DUPLEX_MODE_FULL = (uint8)0x1U
201 ETHTRCV_WUM_DISABLE = (uint8)0x0U,
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DStandardTypes.h148 typedef uint8 StatusType;
156 typedef uint8 Std_ReturnType;
167 uint8 sw_major_version; /**< @brief BSW module software major version */
168 uint8 sw_minor_version; /**< @brief BSW module software minor version */
169 uint8 sw_patch_version; /**< @brief BSW module software patch version */
176 typedef uint8 Std_TransformerErrorCode;
184 …STD_TRANSFORMER_UNSPECIFIED = (uint8)0x00, /**< @brief Transformer of a unspecified transformer cl…
185 STD_TRANSFORMER_SERIALIZER = (uint8)0x01, /**< @brief Transformer of a serializer class. */
186 STD_TRANSFORMER_SAFETY = (uint8)0x02, /**< @brief Transformer of a safety class. */
187 STD_TRANSFORMER_SECURITY = (uint8)0x03, /**< @brief Transformer of a security class. */
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/hal_nxp-3.5.0/s32/drivers/s32ze/Eth_NETC/include/
DNetc_Eth_Ip.h104 Netc_Eth_Ip_StatusType Netc_Eth_Ip_Init(uint8 ctrlIndex, const Netc_Eth_Ip_ConfigType *config);
112 Netc_Eth_Ip_PowerStateType Netc_Eth_Ip_GetPowerState(uint8 CtrlIndex);
121 Netc_Eth_Ip_StatusType Netc_Eth_Ip_EnableController(uint8 ctrlIndex);
133 Netc_Eth_Ip_StatusType Netc_Eth_Ip_DisableController(uint8 ctrlIndex);
159 Netc_Eth_Ip_StatusType Netc_Eth_Ip_GetTxBuff(uint8 ctrlIndex,
160 uint8 ring,
187 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendFrame(uint8 ctrlIndex,
188 uint8 ring,
218 Netc_Eth_Ip_StatusType Netc_Eth_Ip_SendMultiBufferFrame(uint8 ctrlIndex,
219 uint8 ring,
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DNetc_Eth_Ip_Irq.h46 void Netc_Eth_Ip_MSIX_SIMsgEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
49 void Netc_Eth_Ip_0_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
52 void Netc_Eth_Ip_1_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
55 void Netc_Eth_Ip_2_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
58 void Netc_Eth_Ip_3_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
61 void Netc_Eth_Ip_4_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
64 void Netc_Eth_Ip_5_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
67 void Netc_Eth_Ip_6_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
70 void Netc_Eth_Ip_7_MSIX_TxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
73 void Netc_Eth_Ip_0_MSIX_RxEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize);
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DNetc_Eth_Ip_Types.h259 typedef void (*Netc_Eth_Ip_CallbackType)(uint8 Controller);
262 typedef void (*Netc_Eth_Ip_ChCallbackType)(uint8 Controller, uint8 Ring);
268 uint8 lengthCBDR; /*!< Number of command buffer descriptors ring. */
274 uint8 Class; /*!< Class of the command. */
275 uint8 Command; /*!< Type of command. */
276 uint8 Data[30U]; /*!< Data. */
288 uint8 classCommand; /*!< Class of command. See CMD field to determine operation. */
289 uint8 cmd; /*!< Used with class to determine operation. */
355 …uint8 CtrlLogicalIndex; /*!< This member keep the value of controller index for…
362 …uint8 *FirstRxDataBufferAddr[FEATURE_NETC_RX_BDR_COUNT]; /*!< Array with starti…
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/hal_nxp-3.5.0/s32/drivers/s32ze/Can_CANEXCEL/include/
DCanEXCEL_Ip.h81 Canexcel_Ip_StatusType Canexcel_Ip_Init(uint8 instance, const Canexcel_Ip_ConfigType * Config, Cane…
93 Canexcel_Ip_StatusType Canexcel_Ip_SetRxIndividualMask(uint8 instance, uint8 descNo, Canexcel_Ip_Fr…
106 Canexcel_Ip_StatusType Canexcel_Ip_ConfigRx(uint8 instance, uint8 descNo, uint32 msgId, Canexcel_Ip…
117 Canexcel_Ip_StatusType Canexcel_Ip_RxDescriptor(uint8 instance, uint8 descNo, uint32 rxPtrList);
131 Canexcel_Ip_StatusType Canexcel_Ip_ReceiveFD(uint8 instance, uint8 descNo, Canexcel_RxFdMsg * RxMsg…
145 Canexcel_Ip_StatusType Canexcel_Ip_ReceiveXL(uint8 instance, uint8 descNo, Canexcel_RxXlMsg * RxMsg…
159 …_Ip_StatusType Canexcel_Ip_SendFDMsg(uint8 instance, uint8 mbIdx, Canexcel_Ip_DataInfoType * info,…
173 …_Ip_StatusType Canexcel_Ip_SendXLMsg(uint8 instance, uint8 mbIdx, Canexcel_Ip_DataInfoType * info,…
187 Canexcel_Ip_StatusType Canexcel_Ip_GetTransferStatus(uint8 instance, uint8 mbIdx);
197 Canexcel_Ip_StatusType Canexcel_Ip_EnterFreezeMode(uint8 instance);
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DCanEXCEL_Ip_Types.h216 …uint8 sduVcanFilterH; /* Filter SDU/VCAN element in case of mask filter type this is SDU/VCAN valu…
217 …uint8 sduVcanFilterL; /* Filter SDU/VCAN element in case of mask filter type this is mask value, i…
223 uint8 noIdFilters;
224 uint8 noActAddrFilters;
225 uint8 noSduFilters;
226 uint8 noVcanFilters;
236 uint8 priority;
237 uint8 retransmission;
239 …uint8 fd_padding; /**< Set a value for padding. It will be used when the data…
242 uint8 STD;
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/hal_nxp-3.5.0/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip_Irq.c97 static inline void Netc_Eth_Ip_MSIX_Tx(uint8 CtrlIndex);
104 static inline void Netc_Eth_Ip_MSIX_Rx(uint8 CtrlIndex);
110 static inline void Netc_Eth_Ip_MSIX_Tx(uint8 CtrlIndex) in Netc_Eth_Ip_MSIX_Tx()
112 uint8 RingIndex; in Netc_Eth_Ip_MSIX_Tx()
167 static inline void Netc_Eth_Ip_MSIX_Rx(uint8 CtrlIndex) in Netc_Eth_Ip_MSIX_Rx()
169 uint8 RingIndex; in Netc_Eth_Ip_MSIX_Rx()
201 void Netc_Eth_Ip_MSIX_SIMsgEvent(uint8 RxChannelId, const uint32 * RxBuffer, uint8 BufferSize) in Netc_Eth_Ip_MSIX_SIMsgEvent()
203 uint8 CounterRxMsgFromVsi; in Netc_Eth_Ip_MSIX_SIMsgEvent()
204 uint8 RxMsgFromVsiMask; in Netc_Eth_Ip_MSIX_SIMsgEvent()
205 uint8 HashValue; in Netc_Eth_Ip_MSIX_SIMsgEvent()
[all …]
/hal_nxp-3.5.0/s32/soc/s32k344/include/
DPower_Ip_Cfg_Defines.h121 #define POWER_IP_MAX_NUMBER_OF_PARTITIONS ((uint8)3U)
177 #define McuConf_McuResetReasonConf_MCU_POWER_ON_RESET ((uint8)0U)
179 #define McuConf_McuResetReasonConf_MCU_FCCU_FTR_RESET ((uint8)1U)
181 #define McuConf_McuResetReasonConf_MCU_STCU_URF_RESET ((uint8)2U)
183 #define McuConf_McuResetReasonConf_MCU_MC_RGM_FRE_RESET ((uint8)3U)
185 #define McuConf_McuResetReasonConf_MCU_FXOSC_FAIL_RESET ((uint8)4U)
187 #define McuConf_McuResetReasonConf_MCU_PLL_LOL_RESET ((uint8)5U)
189 #define McuConf_McuResetReasonConf_MCU_CORE_CLK_FAIL_RESET ((uint8)6U)
191 #define McuConf_McuResetReasonConf_MCU_AIPS_PLAT_CLK_FAIL_RESET ((uint8)7U)
193 #define McuConf_McuResetReasonConf_MCU_HSE_CLK_FAIL_RESET ((uint8)8U)
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/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Sfdp.c493 uint8 paramTableLength_basic;
494 uint8 paramTableLength_4badd;
495 uint8 paramTableLength_xspi1;
496 uint8 paramTableLength_srmap;
497 uint8 paramTableLength_2dopi;
516 static uint8 initOpCount; /* Current number of operations in the initial operation…
517 static uint8 basicAddrBits; /* Current number of operations in the initial operation…
518 static uint8 modeIndex; /* Index of the selected read mode …
557 static uint8 eraseInstDword[4U] = {
563 static uint8 eraseInstShift[4U] = {
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/hal_nxp-3.5.0/s32/drivers/s32k3/Mcl/include/
DEmios_Mcl_Ip.h128 void Emios_Mcl_Ip_EnableChannel(uint8 Instance, uint8 HwChannel);
137 void Emios_Mcl_Ip_DisableChannel(uint8 Instance, uint8 HwChannel);
152 void Emios_Mcl_Ip_ComparatorTransferEnable(uint8 Instance, uint32 ChannelMask);
167 void Emios_Mcl_Ip_ComparatorTransferDisable(uint8 Instance, uint32 ChannelMask);
176 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Deinit(uint8 Instance);
186 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Init(uint8 Instance, const Emios_Mcl_Ip_ConfigType *const Co…
204 void Emios_Mcl_Ip_SetReloadInterval(uint8 HwInstance, uint8 HwChannel, uint8 Interval);
214 boolean Emios_Mcl_Ip_ValidateChannel(uint8 HwInstance, uint8 HwChannel);
224 Emios_Ip_CommonStatusType Emios_Mcl_Ip_SetCounterBusPeriod(uint8 HwInstance, uint8 HwChannel, uint3…
234 uint32 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel);
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/hal_nxp-3.5.0/s32/drivers/s32ze/Uart/include/
DLinflexd_Uart_Ip.h117 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_SetBaudrate(const uint8 Instance,
132 void Linflexd_Uart_Ip_GetBaudrate(const uint8 Instance, uint32 * ConfiguredBaudRate);
143 void Linflexd_Uart_Ip_Init(const uint8 Instance, const Linflexd_Uart_Ip_UserConfigType * UserConfig…
154 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_Deinit(const uint8 Instance);
167 void Linflexd_Uart_Ip_SetTxBuffer(const uint8 Instance,
168 const uint8 * TxBuff,
183 void Linflexd_Uart_Ip_SetRxBuffer(const uint8 Instance,
184 uint8 * RxBuff,
196 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_AbortReceivingData(const uint8 Instance);
207 Linflexd_Uart_Ip_StatusType Linflexd_Uart_Ip_AbortSendingData(const uint8 Instance);
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/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/include/
DStandardTypes.h148 typedef uint8 StatusType;
156 typedef uint8 Std_ReturnType;
167 uint8 sw_major_version; /**< @brief BSW module software major version */
168 uint8 sw_minor_version; /**< @brief BSW module software minor version */
169 uint8 sw_patch_version; /**< @brief BSW module software patch version */
176 typedef uint8 Std_TransformerErrorCode;
184 …STD_TRANSFORMER_UNSPECIFIED = (uint8)0x00, /**< @brief Transformer of a unspecified transformer cl…
185 STD_TRANSFORMER_SERIALIZER = (uint8)0x01, /**< @brief Transformer of a serializer class. */
186 STD_TRANSFORMER_SAFETY = (uint8)0x02, /**< @brief Transformer of a safety class. */
187 STD_TRANSFORMER_SECURITY = (uint8)0x03, /**< @brief Transformer of a security class. */
[all …]
/hal_nxp-3.5.0/s32/drivers/s32ze/Gpt/include/
DStm_Ip.h179 uint32 Stm_Ip_GetInterruptFlag(uint8 instance, uint8 channel);
195 void Stm_Ip_Init(uint8 instance, const Stm_Ip_InstanceConfigType *configPtr);
210 void Stm_Ip_InitChannel(uint8 instance, const Stm_Ip_ChannelConfigType *configPtr);
223 void Stm_Ip_Deinit(uint8 instance);
238 void Stm_Ip_StartCounting(uint8 instance, uint8 channel, uint32 compareValue);
254 void Stm_Ip_StartCountingAbsolute(uint8 instance, uint8 channel, uint32 compareValue);
269 void Stm_Ip_StartTimer(uint8 instance, uint32 startValue);
280 void Stm_Ip_StopTimer(uint8 instance);
291 void Stm_Ip_EnableChannel(uint8 instance, uint8 channel);
302 void Stm_Ip_DisableChannel(uint8 instance, uint8 channel);
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/hal_nxp-3.5.0/s32/drivers/s32ze/Icu/include/
DSiul2_Icu_Ip.h143 Siul2_Icu_Ip_StatusType Siul2_Icu_Ip_DeInit(uint8 instance);
159 Siul2_Icu_Ip_StatusType Siul2_Icu_Ip_Init(uint8 instance, const Siul2_Icu_Ip_ConfigType* userConfig…
170 void Siul2_Icu_Ip_SetActivationCondition(uint8 instance, uint8 hwChannel, Siul2_Icu_Ip_EdgeType edg…
180 boolean Siul2_Icu_Ip_GetInputState(uint8 instance, uint8 hwChannel);
191 void Siul2_Icu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel);
201 void Siul2_Icu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel);
212 void Siul2_Icu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel);
223 void Siul2_Icu_Ip_SetNormalMode(uint8 instance, uint8 HwChannel);
236 void Siul2_Icu_Ip_SetClockMode(uint8 instance, Siul2_Icu_Ip_ClockModeType mode);
246 void Siul2_Icu_Ip_EnableNotification(uint8 instance, uint8 hwChannel);
[all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_Types.h309 …uint8 referenceCounter; /*!< Select the "n+1" interval of DLL phase detection and refere…
310 …uint8 resolution; /*!< Minimum resolution for DLL phase detector …
311 …uint8 coarseDelay; /*!< Coarse delay DLL slave delay chain …
312 …uint8 fineDelay; /*!< Fine delay DLL slave delay chain …
313 …uint8 tapSelect; /*!< Selects the Nth tap provided by the slave delay-chain …
324 …uint8 masters[QSPI_IP_AHB_BUFFERS]; /*!< List of AHB masters assigned to each buffer */
381 uint8 Mask;
382 uint8 DomainId;
415 uint8 ExclusiveAccessOwner;
447 …uint8 clockRefDiv; /*!< Divider value for internal reference clock …
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/hal_nxp-3.5.0/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip_Irq.c145 extern uint8 eMios_Icu_Ip_IndexInChState[EMIOS_ICU_IP_INSTANCE_COUNT][EMIOS_ICU_IP_NUM_OF_CHANNELS];
187 static inline void Emios_Icu_Ip_ReportEvents(uint8 instance, uint8 hwChannel, boolean bOverflow);
197 static inline void Emios_Icu_Ip_ReportOverflow(uint8 instance, uint8 hwChannel, boolean bOverflow);
211 const uint8 instance,
212 const uint8 hwChannel
227 const uint8 instance,
228 const uint8 hwChannel
244 const uint8 instance,
245 const uint8 hwChannel,
262 const uint8 instance,
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