Home
last modified time | relevance | path

Searched refs:SelectorIndex (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Selector.c151 uint32 SelectorIndex; in Clock_Ip_ResetCgmXCscCssClkswSwip() local
157 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_ResetCgmXCscCssClkswSwip()
160 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswSwip()
161 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssClkswSwip()
166 (void)SelectorIndex; in Clock_Ip_ResetCgmXCscCssClkswSwip()
176 uint32 SelectorIndex; in Clock_Ip_SetCgmXCscCssClkswSwip() local
191 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_SetCgmXCscCssClkswSwip()
198 …if (SelectorValue != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & SelectorMask) >> SelectorSh… in Clock_Ip_SetCgmXCscCssClkswSwip()
205 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
209 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()
[all …]
DClock_Ip_DividerTrigger.c128 uint32 SelectorIndex; in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() local
133 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
138 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
142 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
149 (void)SelectorIndex; in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
156 uint32 SelectorIndex; in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat() local
167 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
172 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG = MC_CGM_MUX_DIV_TRIG_TRIGGER(CLOCK_IP_TRIG… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
178 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
194 (void)SelectorIndex; in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
DClock_Ip_Divider.c139 uint32 SelectorIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local
155 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
163 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
166 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
169 if((Instance == 0U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
173 else if((Instance == 4U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
188 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
199 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
203 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
215 (void)SelectorIndex; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Selector.c153 uint32 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_ResetCgmXCscCssClkswSwip() local
157 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswSwip()
158 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssClkswSwip()
166 uint32 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_SetCgmXCscCssClkswSwip() local
179 …if (SelectorValue != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & SelectorMask) >> SelectorSh… in Clock_Ip_SetCgmXCscCssClkswSwip()
186 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
190 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()
194 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()
202 …_IP_MC_CGM_MUX_CSS_CLK_SW_NOT_REQUESTED == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM… in Clock_Ip_SetCgmXCscCssClkswSwip()
212 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
[all …]
DClock_Ip_Divider.c137 uint32 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase() local
153 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
156 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
159 if((Instance == 0U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
163 else if((Instance == 4U) && (SelectorIndex == 2U) && (DividerIndex == 2U)) in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
178 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
189 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
193 … Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
208 uint32 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger() local
224 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
[all …]
DClock_Ip_DividerTrigger.c128 uint32 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat() local
133 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
137 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
144 uint32 SelectorIndex = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_SELECTOR_INDEX]; in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat() local
155 …Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG = MC_CGM_MUX_DIV_TRIG_TRIGGER(CLOCK_IP_TRIG… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
161 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()