/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/ |
D | fsl_dmic_dma.c | 132 bool loopEnd = false, intA = true; in DMIC_TransferReceiveDMA() local 149 … DMA_CHANNEL_XFER(currentTransfer->linkTransfer != NULL ? 1UL : 0UL, 0UL, intA, !intA, in DMIC_TransferReceiveDMA() 154 intA = intA == true ? false : true; in DMIC_TransferReceiveDMA() 198 …DMA_CHANNEL_XFER(xfer->linkTransfer == NULL ? 0UL : 1UL, 0UL, intA, !intA, xfer->dataWidth, interl… in DMIC_TransferReceiveDMA()
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D | fsl_i2s_dma.c | 47 volatile bool intA; /*!< If next scheduled DMA transfer will cause interrupt A or B */ member 328 privateHandle->intA = false; in I2S_TransferAbortDMA() 470 privateHandle->intA = false; in I2S_StartTransferDMA() 533 bool intA = false; in I2S_AddTransferDMA() local 542 intA = privateHandle->intA; in I2S_AddTransferDMA() 574 …DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transfer… in I2S_AddTransferDMA() 580 privateHandle->intA = !privateHandle->intA; in I2S_AddTransferDMA()
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D | fsl_spi_dma.c | 294 tmp_xfercfg.intA = true; in SPI_MasterTransferDMA() 312 xferConfig.xfercfg.intA = false; in SPI_MasterTransferDMA() 339 tmp_xfercfg.intA = true; in SPI_MasterTransferDMA() 357 xferConfig.xfercfg.intA = false; in SPI_MasterTransferDMA()
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D | fsl_dma.h | 109 #define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) … argument 111 …DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | … 159 … bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ member
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D | fsl_dma.c | 238 xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); in DMA_SetupXferCFG() 593 config->xfercfg.intA = true; in DMA_PrepareTransfer()
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/hal_nxp-2.7.6/mcux/drivers/lpc/ |
D | fsl_dmic_dma.c | 132 bool loopEnd = false, intA = true; in DMIC_TransferReceiveDMA() local 149 … DMA_CHANNEL_XFER(currentTransfer->linkTransfer != NULL ? 1UL : 0UL, 0UL, intA, !intA, in DMIC_TransferReceiveDMA() 154 intA = intA == true ? false : true; in DMIC_TransferReceiveDMA() 198 …DMA_CHANNEL_XFER(xfer->linkTransfer == NULL ? 0UL : 1UL, 0UL, intA, !intA, xfer->dataWidth, interl… in DMIC_TransferReceiveDMA()
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D | fsl_i2s_dma.c | 47 volatile bool intA; /*!< If next scheduled DMA transfer will cause interrupt A or B */ member 328 privateHandle->intA = false; in I2S_TransferAbortDMA() 470 privateHandle->intA = false; in I2S_StartTransferDMA() 533 bool intA = false; in I2S_AddTransferDMA() local 542 intA = privateHandle->intA; in I2S_AddTransferDMA() 574 …DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transfer… in I2S_AddTransferDMA() 580 privateHandle->intA = !privateHandle->intA; in I2S_AddTransferDMA()
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D | fsl_spi_dma.c | 294 tmp_xfercfg.intA = true; in SPI_MasterTransferDMA() 312 xferConfig.xfercfg.intA = false; in SPI_MasterTransferDMA() 339 tmp_xfercfg.intA = true; in SPI_MasterTransferDMA() 357 xferConfig.xfercfg.intA = false; in SPI_MasterTransferDMA()
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D | fsl_dma.h | 109 #define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) … argument 111 …DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | … 159 … bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ member
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D | fsl_dma.c | 238 xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA); in DMA_SetupXferCFG() 593 config->xfercfg.intA = true; in DMA_PrepareTransfer()
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