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Searched refs:XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h30874 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
30880 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h33803 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
33809 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h45928 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
45934 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h45910 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
45916 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h42063 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
42069 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h51862 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
51868 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h44471 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
44477 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h54521 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
54527 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h54447 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) macro
54453 …(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK)
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h39938 #define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK 0x20u macro