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Searched refs:XTALOSC24M (Results 1 – 25 of 28) sorted by relevance

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/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
Dfsl_clock.c261 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL) in CLOCK_InitExternalClk()
295 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
299 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
308 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
316 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h921 …return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 240000… in CLOCK_GetOscFreq()
DMIMXRT1011.h31356 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) macro
31360 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
Dfsl_clock.c195 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL) in CLOCK_InitExternalClk()
229 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
233 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
242 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
250 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h984 …return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 240000… in CLOCK_GetOscFreq()
DMIMXRT1015.h34285 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) macro
34289 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
Dfsl_clock.c165 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
199 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
203 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
212 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
220 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1096 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
DMIMXRT1051.h42545 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) macro
42549 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
Dfsl_clock.c194 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL) in CLOCK_InitExternalClk()
228 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
232 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
241 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
249 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1120 …return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 240000… in CLOCK_GetOscFreq()
DMIMXRT1021.h46519 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) macro
46523 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
Dfsl_clock.c165 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
199 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
203 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
212 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
220 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1117 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
Dfsl_clock.c194 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0UL) in CLOCK_InitExternalClk()
228 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
232 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
241 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
249 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1124 …return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 240000… in CLOCK_GetOscFreq()
DMIMXRT1024.h46501 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) macro
46505 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
Dfsl_clock.c195 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
229 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
233 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
242 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
250 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1238 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
DMIMXRT1052.h52453 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) macro
52457 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
Dfsl_clock.c196 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
230 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
234 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
243 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
251 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1264 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
Dfsl_clock.c196 while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0U) in CLOCK_InitExternalClk()
230 XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; in CLOCK_SwitchOsc()
234 XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; in CLOCK_SwitchOsc()
243 XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_InitRcOsc24M()
251 XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; in CLOCK_DeinitRcOsc24M()
Dfsl_clock.h1264 …return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_x… in CLOCK_GetOscFreq()
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h40223 #define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) macro
40224 #define XTALOSC24M_BASE_PTR (XTALOSC24M)
40228 #define XTALOSC24M_BASE_PTRS { XTALOSC24M }

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