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Searched refs:USBPHY2 (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
Dfsl_clock.c1751 USBPHY2->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhs1PhyPllClock()
1753 USBPHY2->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbhs1PhyPllClock()
1813 USBPHY2->PLL_SIC = (USBPHY2->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbhs1PhyPllClock()
1815 USBPHY2->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbhs1PhyPllClock()
1816 USBPHY2->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbhs1PhyPllClock()
1818 USBPHY2->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhs1PhyPllClock()
1819 USBPHY2->PWD_SET = 0x0; in CLOCK_EnableUsbhs1PhyPllClock()
1821 while (0UL == (USBPHY2->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbhs1PhyPllClock()
1832 USBPHY2->PLL_SIC_CLR = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_DisableUsbhs1PhyPllClock()
1833 USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs1PhyPllClock()
DMIMXRT1176_cm7.h98234 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) macro
98238 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
DMIMXRT1176_cm4.h99165 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) macro
99169 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
Dfsl_clock.c1228 USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs1PhyPllClock()
1229 USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs1PhyPllClock()
1231 USBPHY2->PWD = 0; in CLOCK_EnableUsbhs1PhyPllClock()
1232 USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs1PhyPllClock()
1245 USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs1PhyPllClock()
DMIMXRT1051.h38219 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) macro
38223 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
Dfsl_clock.c1249 USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs1PhyPllClock()
1250 USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs1PhyPllClock()
1252 USBPHY2->PWD = 0; in CLOCK_EnableUsbhs1PhyPllClock()
1253 USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs1PhyPllClock()
1266 USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs1PhyPllClock()
DMIMXRT1061.h40627 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) macro
40631 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
Dfsl_clock.c1340 USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs1PhyPllClock()
1341 USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs1PhyPllClock()
1343 USBPHY2->PWD = 0; in CLOCK_EnableUsbhs1PhyPllClock()
1344 USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs1PhyPllClock()
1357 USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs1PhyPllClock()
DMIMXRT1052.h47496 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) macro
47500 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
Dfsl_clock.c1357 USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs1PhyPllClock()
1358 USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs1PhyPllClock()
1360 USBPHY2->PWD = 0; in CLOCK_EnableUsbhs1PhyPllClock()
1361 USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs1PhyPllClock()
1374 USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs1PhyPllClock()
DMIMXRT1062.h50155 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) macro
50159 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
Dfsl_clock.c1357 USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs1PhyPllClock()
1358 USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs1PhyPllClock()
1360 USBPHY2->PWD = 0; in CLOCK_EnableUsbhs1PhyPllClock()
1361 USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs1PhyPllClock()
1374 USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs1PhyPllClock()
DMIMXRT1064.h50081 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) macro
50085 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h38681 #define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) macro
38682 #define USBPHY2_BASE_PTR (USBPHY2)
38686 #define USBPHY_BASE_PTRS { USBPHY1, USBPHY2 }