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Searched refs:TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h25237 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
25243 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h27551 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
27557 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h36827 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
36833 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h36809 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
36815 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h33654 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
33660 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h42197 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
42203 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h36062 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
36068 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h44856 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
44862 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h44782 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) macro
44788 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK)
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h34938 #define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK 0x4u macro