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Searched refs:TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h25268 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
25274 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h27582 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
27588 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h36863 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
36869 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h36845 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
36851 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h33685 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
33691 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h42233 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
42239 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h36093 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
36099 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h44892 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
44898 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h44818 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) macro
44824 …(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK)
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h34951 #define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK 0x4u macro