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Searched refs:refclk_phase (Results 1 – 1 of 1) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr.c1053 uint32_t bclk_phase, bclk90_phase,refclk_phase; in ddr_setup() local
1384 refclk_phase = (j % 8U) << 2U; in ddr_setup()
1385 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); in ddr_setup()
1386 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase | refclk_phase); in ddr_setup()
1387 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); in ddr_setup()
1542 refclk_phase =((refclk_offset+min_refclk) & 0x7U)<<2U; in ddr_setup()
1543 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); in ddr_setup()
1544 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00000003UL | bclk_phase | bclk90_phase | refclk_phase); in ddr_setup()
1545 … MSS_SCB_DDR_PLL->PLL_PHADJ = (0x00004003UL | bclk_phase | bclk90_phase | refclk_phase); in ddr_setup()