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Searched refs:MEC5_ECIA_INFO (Results 1 – 25 of 30) sorted by relevance

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/hal_microchip-latest/mec5/drivers/
Dmec_dmac.c30 #define MEC_DMAC_CHAN0_ECIA_INFO MEC5_ECIA_INFO(14, 0, 6, 24)
31 #define MEC_DMAC_CHAN1_ECIA_INFO MEC5_ECIA_INFO(14, 1, 6, 25)
32 #define MEC_DMAC_CHAN2_ECIA_INFO MEC5_ECIA_INFO(14, 2, 6, 26)
33 #define MEC_DMAC_CHAN3_ECIA_INFO MEC5_ECIA_INFO(14, 3, 6, 27)
34 #define MEC_DMAC_CHAN4_ECIA_INFO MEC5_ECIA_INFO(14, 4, 6, 28)
35 #define MEC_DMAC_CHAN5_ECIA_INFO MEC5_ECIA_INFO(14, 5, 6, 29)
36 #define MEC_DMAC_CHAN6_ECIA_INFO MEC5_ECIA_INFO(14, 6, 6, 30)
37 #define MEC_DMAC_CHAN7_ECIA_INFO MEC5_ECIA_INFO(14, 7, 6, 31)
38 #define MEC_DMAC_CHAN8_ECIA_INFO MEC5_ECIA_INFO(14, 8, 6, 32)
39 #define MEC_DMAC_CHAN9_ECIA_INFO MEC5_ECIA_INFO(14, 9, 6, 33)
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Dmec_wktimer.c52 MEC5_ECIA_INFO(MEC_WKTMR_GIRQ, MEC_WKTMR_WK_ALARM_GIRQ_POS, \
56 MEC5_ECIA_INFO(MEC_WKTMR_GIRQ, MEC_WKTMR_SUB_WK_ALARM_GIRQ_POS, \
60 MEC5_ECIA_INFO(MEC_WKTMR_GIRQ, MEC_WKTMR_ONE_SEC_GIRQ_POS, \
64 MEC5_ECIA_INFO(MEC_WKTMR_GIRQ, MEC_WKTMR_SUB_SEC_GIRQ_POS, \
68 MEC5_ECIA_INFO(MEC_WKTMR_GIRQ, MEC_WKTMR_SYS_PWR_PRES_GIRQ_POS, \
Dmec_acpi_ec.c31 #define MEC_ACPI_EC0_IBF_ECIA_INFO MEC5_ECIA_INFO(15, 5, 7, 45)
32 #define MEC_ACPI_EC0_OBE_ECIA_INFO MEC5_ECIA_INFO(15, 6, 7, 46)
33 #define MEC_ACPI_EC1_IBF_ECIA_INFO MEC5_ECIA_INFO(15, 7, 7, 47)
34 #define MEC_ACPI_EC1_OBE_ECIA_INFO MEC5_ECIA_INFO(15, 8, 7, 48)
35 #define MEC_ACPI_EC2_IBF_ECIA_INFO MEC5_ECIA_INFO(15, 9, 7, 49)
36 #define MEC_ACPI_EC2_OBE_ECIA_INFO MEC5_ECIA_INFO(15, 10, 7, 50)
37 #define MEC_ACPI_EC3_IBF_ECIA_INFO MEC5_ECIA_INFO(15, 11, 7, 51)
38 #define MEC_ACPI_EC3_OBE_ECIA_INFO MEC5_ECIA_INFO(15, 12, 7, 52)
39 #define MEC_ACPI_EC4_IBF_ECIA_INFO MEC5_ECIA_INFO(15, 13, 7, 53)
40 #define MEC_ACPI_EC4_OBE_ECIA_INFO MEC5_ECIA_INFO(15, 14, 7, 54)
Dmec_tach.c20 #define MEC_TACH0_ECIA_INFO MEC5_ECIA_INFO(17, 1, 9, 71)
21 #define MEC_TACH1_ECIA_INFO MEC5_ECIA_INFO(17, 2, 9, 72)
22 #define MEC_TACH2_ECIA_INFO MEC5_ECIA_INFO(17, 3, 9, 73)
23 #define MEC_TACH3_ECIA_INFO MEC5_ECIA_INFO(17, 4, 9, 159)
Dmec_btimer.c29 #define MEC_BTIMER0_ECIA_INFO MEC5_ECIA_INFO(23, 0, 14, 136)
30 #define MEC_BTIMER1_ECIA_INFO MEC5_ECIA_INFO(23, 1, 14, 137)
31 #define MEC_BTIMER2_ECIA_INFO MEC5_ECIA_INFO(23, 2, 14, 138)
32 #define MEC_BTIMER3_ECIA_INFO MEC5_ECIA_INFO(23, 3, 14, 139)
33 #define MEC_BTIMER4_ECIA_INFO MEC5_ECIA_INFO(23, 4, 14, 140)
34 #define MEC_BTIMER5_ECIA_INFO MEC5_ECIA_INFO(23, 5, 14, 141)
Dmec_ps2.c23 #define MEC_PS2_0_ECIA_INFO MEC5_ECIA_INFO(18, 10, 10, 100)
24 #define MEC_PS2_1_ECIA_INFO MEC5_ECIA_INFO(18, 11, 10, 101)
37 #define MEC_PS2_WAKE_0A_ECIA_INFO MEC5_ECIA_INFO(21, 13, 18, 129)
38 #define MEC_PS2_WAKE_0B_ECIA_INFO MEC5_ECIA_INFO(21, 13, 19, 130)
39 #define MEC_PS2_WAKE_1B_ECIA_INFO MEC5_ECIA_INFO(21, 13, 21, 132)
Dmec_emi.c22 #define MEC_EMI0_ECIA_INFO MEC5_ECIA_INFO(15, 2, 7, 42)
23 #define MEC_EMI1_ECIA_INFO MEC5_ECIA_INFO(15, 3, 7, 43)
24 #define MEC_EMI2_ECIA_INFO MEC5_ECIA_INFO(15, 4, 7, 44)
Dmec_htimer.c21 #define MEC_HTMR0_ECIA_INFO MEC5_ECIA_INFO(MEC_HTMR_GIRQ, MEC_HTMR0_GIRQ_POS, 14, 112)
23 #define MEC_HTMR1_ECIA_INFO MEC5_ECIA_INFO(MEC_HTMR_GIRQ, MEC_HTMR0_GIRQ_POS, 14, 113)
Dmec_bbled.c31 #define MEC_BBLED0_ECIA_INFO MEC5_ECIA_INFO(23, 0, 14, 136)
32 #define MEC_BBLED1_ECIA_INFO MEC5_ECIA_INFO(23, 1, 14, 137)
33 #define MEC_BBLED2_ECIA_INFO MEC5_ECIA_INFO(23, 2, 14, 138)
34 #define MEC_BBLED3_ECIA_INFO MEC5_ECIA_INFO(23, 3, 14, 139)
Dmec_espi_pc.c17 #define MEC_ESPI_PC_ECIA_INFO MEC5_ECIA_INFO(19, 0, 11, 103)
18 #define MEC_ESPI_LTR_ECIA_INFO MEC5_ECIA_INFO(19, 3, 11, 106)
Dmec_bclink.c26 MEC5_ECIA_INFO(MEC_BCL_GIRQ, MEC_BCL_BUSY_CLR_GIRQ_POS, \
29 MEC5_ECIA_INFO(MEC_BCL_GIRQ, MEC_BCL_ERR_GIRQ_POS, MEC_BCL_GIRQ_AGGR_NVIC, MEC_BCL_ERR_NVIC)
Dmec_kbc.c21 #define MEC_KBC_OBE_ECIA_INFO MEC5_ECIA_INFO(15, 18, 7, 58)
22 #define MEC_KBC_IBF_ECIA_INFO MEC5_ECIA_INFO(15, 19, 7, 60)
Dmec_espi_oob.c25 #define MEC_ESPI_OOB_UP_ECIA_INFO MEC5_ECIA_INFO(MEC5_ESPI_GIRQ, MEC5_ESPI_OOB_UP_GIRQ_POS, \
28 #define MEC_ESPI_OOB_DN_ECIA_INFO MEC5_ECIA_INFO(MEC5_ESPI_GIRQ, MEC5_ESPI_OOB_DN_GIRQ_POS, \
Dmec_ecia_api.h36 #define MEC5_ECIA_INFO(g, gb, na, nd) \ macro
Dmec_uart.c26 #define MEC_UART0_ECIA_INFO MEC5_ECIA_INFO(15, 0, 7, 40)
27 #define MEC_UART1_ECIA_INFO MEC5_ECIA_INFO(15, 1, 7, 41)
28 #define MEC_UART2_ECIA_INFO MEC5_ECIA_INFO(15, 25, 7, 183)
29 #define MEC_UART3_ECIA_INFO MEC5_ECIA_INFO(15, 26, 7, 184)
Dmec_rtimer.c19 #define MEC_RTMR_ECIA_INFO MEC5_ECIA_INFO(MEC_RTMR_GIRQ, MEC_RTMR_GIRQ_POS, 14, 111)
Dmec_adc.c19 #define MEC_ADC_SM_ECIA_INFO MEC5_ECIA_INFO(MEC_ADC_GIRQ, MEC_ADC_SM_GIRQ_POS, 9, 78)
20 #define MEC_ADC_RM_ECIA_INFO MEC5_ECIA_INFO(MEC_ADC_GIRQ, MEC_ADC_RM_GIRQ_POS, 9, 79)
Dmec_espi_taf.c35 MEC5_ECIA_INFO(MEC_ESPI_TAF_GIRQ, MEC_ESPI_TAF_DONE_GIRQ_POS, MEC_ESPI_TAF_GIRQ_AGGR_NVIC,\
38 MEC5_ECIA_INFO(MEC_ESPI_TAF_GIRQ, MEC_ESPI_TAF_ERR_GIRQ_POS, MEC_ESPI_TAF_GIRQ_AGGR_NVIC,\
Dmec_i2c.c77 #define MEC_I2C_SMB0_ECIA_INFO MEC5_ECIA_INFO(13, 0, 5, 20)
78 #define MEC_I2C_SMB1_ECIA_INFO MEC5_ECIA_INFO(13, 1, 5, 21)
79 #define MEC_I2C_SMB2_ECIA_INFO MEC5_ECIA_INFO(13, 2, 5, 22)
80 #define MEC_I2C_SMB3_ECIA_INFO MEC5_ECIA_INFO(13, 3, 5, 23)
81 #define MEC_I2C_SMB4_ECIA_INFO MEC5_ECIA_INFO(13, 4, 5, 158)
Dmec_rom_rng.c24 #define MEC_NDRNG_ECIA_INFO MEC5_ECIA_INFO(MEC_NDRNG_GIRQ, MEC_NDRNG_GIRQ_POS, \
Dmec_kscan.c22 #define MEC_KSCAN_ECIA_INFO MEC5_ECIA_INFO(MEC_KSCAN_GIRQ, MEC_KSCAN_GIRQ_POS, \
Dmec_wdt.c27 #define MEC5_WDT0_ECIA_INFO MEC5_ECIA_INFO(21, 2, 13, 171)
Dmec_mailbox.c20 #define MEC_MBOX0_ECIA_INFO MEC5_ECIA_INFO(15, 20, 7, 60)
Dmec_bdp.c21 MEC5_ECIA_INFO(MEC_BDP_GIRQ, MEC_BDP_GIRQ_POS, MEC_BDP_AGGR_NVIC, MEC_BDP_NVIC)
Dmec_espi_fc.c20 #define MEC_ESPI_FC_ECIA_INFO MEC5_ECIA_INFO(19, 6, 11, 109)

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